tfra08c13 ETC-unknow, tfra08c13 Datasheet - Page 39

• Manufacturer Part Number: tfra08c13
• Description: Tfra08c13 Octal T1/e1 Framer
• Manufacturer: ETC-unknow

Preliminary Data Sheet
October 2000
Lucent Technologies Inc.
Lucent Technologies Inc.
Frame Formats
Table 11. SLC -96 Line Switch Message Codes
Internal SLC -96 Stack Source. Optionally, a SLC -96 FDL stack may be used to insert and correspondingly extract
the FDL information in the SLC -96 frame format.
The transmit SLC -96 FDL bits are sourced from the transmit framer SLC -96 FDL stack. The SLC -96 FDL stack
(see FRM_PR31—FRM_PR35) consists of five 8-bit registers that contain the SLC -96 FS and D-bit information as
shown in Table 12. The transmit stack data is transmitted to the line when the stack enable mode is active in the
parameter registers FRM_PR21 bit 6 = 1 and FRM_PR29 bit 5—bit 7 = x10 (binary).
The receive SLC -96 stack data is received when the receive framer is in the superframe alignment state. In the
SLC -96 mode, while in the loss of superframe alignment (LSFA) state, updating of the receive framer SLC -96 stack
is halted and neither the receive stack interrupt nor receive stack flag are asserted.
Table 12. Transmit and Receive SLC -96 Stack Structure
Bit 5—bit 0 of the first 2 bytes of the SLC -96 FDL stack in Table 12 are transmitted to the line as the SLC -96 F
sequence. Bit 7 of the third stack register is transmitted as the C
(SPB1, SPB2, SPB3, and SPB4) are taken directly from the transmit stack. The protocol for accessing the SLC -96
stack information for the transmit and receive framer is described below. The transmit SLC -96 stack must be written
with valid data when transmitting stack data.
The device indicates that it is ready for an update of its transmit stack by setting register FRM_SR4 bit 5 ( SLC -96
transmit FDL stack ready) high. At this time, the system has about 9 ms to update the stack. Data written to the
stack during this interval will be transmitted during the next SLC -96 superframe D-bit interval. By reading bit 5 in
register SR4, the system clears this bit so that it can indicate the next time the transmit stack is ready. If the trans-
mit stack is not updated, then the content of the stack is retransmitted to the line. The start of the SLC -96 36-frame
F
bytes must be programmed as shown in Table 12. Programming any other state into these two registers disables
the proper transmission of the SLC -96 D bits. Once programmed correctly, the transmit SLC -96 D-bit stack is trans-
mitted synchronous to the transmit SLC -96 superframe structure.
On the receive side, the device indicates that it has received data in the receive FDL stack (registers FRM_SR54—
FRM_SR58) by setting bit 4 in register FRM_SR4 ( SLC -96 receive FDL stack ready) high. The system then has
about 9 ms to read the content of the stack before it is updated again (old data lost). By reading bit 4 in register
FRM_SR4, the system clears this bit so that it can indicate the next time the receive stack is ready. As explained
above, the SLC -96 receive stack is not updated when superframe alignment is lost.
Register Number Bit 7 (MSB)
S
S
1
1
1
1
1
0
0
0
interval of the transmit framer is a function of the first 2 bytes of the SLC -96 transmit stack registers. These
1
1 (LSR)
S
1
1
1
1
0
1
1
0
2
3
4
5
2
S
1
1
0
0
1
0
0
1
3
S
1
0
1
0
0
1
0
0
(continued)
4
M
C
C
0
0
1
9
3
Switch line B transmit and receive
Switch line B transmit and receive
Switch line B transmit and receive
Bit 6
C
C
A
0
0
10
Switch line C transmit
Switch line D transmit
Switch line B transmit
2
1
Switch line A receive
Code Definition
Bit 5
Idle
C
C
A
0
0
11
2
3
SPB
Bit 4
C
S
0
0
1
4
1
= 0 SPB
1
bit of the SLC -96 D sequence. The spoiler bits
Bit 3
C
S
TFRA08C13 OCTAL T1/E1 Framer
0
0
2
2
5
= 1 SPB
Bit 2
C
S
1
1
3
6
3
= 0
Bit 1
M
C
S
1
1
7
4
1
Bit 0 (LSB)
SPB
M
C
1
1
4
8
2
= 1
S
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