tfra08c13 ETC-unknow, tfra08c13 Datasheet - Page 56

• Manufacturer Part Number: tfra08c13
• Description: Tfra08c13 Octal T1/e1 Framer
• Manufacturer: ETC-unknow

TFRA08C13 OCTAL T1/E1 Framer
Frame Formats
CEPT Loss of Time Slot 16 Multiframe Align-
ment (LTS16MFA)
Loss of basic frame alignment forces the receive framer
into a loss of time slot 16 signaling multiframe align-
ment state. In addition, as defined in ITU Rec. G.732
Section 5.2, time slot 16 signaling multiframe is
assumed lost when two consecutive time slot 16 multi-
frame 4-bit all-zero patterns is received with an error. In
addition, the time slot 16 multiframe is assumed lost
when, for a period of two multiframes, all bits in time
slot 16 are in state 0. This state is reported by way of
the status registers FRM_SR1 bit 1. Once basic frame
alignment is achieved, the receive framer will initiate a
search for the time slot 16 multiframe alignment. During
a loss of time slot 16 multiframe alignment state, the
following occurs:
CEPT Loss of Time Slot 16 Multiframe Align-
ment Recovery Algorithm
The time slot 16 multiframe alignment recovery algo-
rithm is as described in ITU Rec. G.732 Section 5.2.
The recommendation states that if a condition of
assumed frame alignment has been achieved, time slot
16 multiframe alignment is deemed to have occurred
when the 4-bit time slot 16 multiframe pattern of 0000
is found in time slot 16 for the first time, and the preced-
ing time slot 16 contained at least one bit in the binary
1 state.
56
The updating of the signaling data is halted.
The received control bits forced to the binary 1 state.
The received remote multiframe alarm indication sta-
tus bit is forced to the binary 0 state.
Optionally, the transmit framer can transmit to the
line the time slot 16 signaling remote multiframe
alarm if register FRM_PR41 bit 4 is set to 1.
Optionally, the transmit framer can transmit the alarm
indication signal (AIS) in the system transmit time
slot 16 data if register FRM_PR44 bit 6 is set to 1.
(continued)
CEPT Time Slot 0 FAS/NOT FAS Control
Bits
FAS/NOT FAS Si- and E-Bit Source
The Si bit can be used as an 8 kbits/s data link to and
from the remote end, or in the CRC-4 mode, it can be
used to provide added protection against false frame
alignment. The sources for the Si bits that are transmit-
ted to the line are the following:
* Whenever bits (e.g., Si, Sa, etc.) are transmitted from the system
transparently, FRM_PR29 must first be momentarily written to
001xxxxx (binary). Otherwise, the transmit framer will not be able
to locate the biframe alignment.
CEPT with no CRC-4 and FRM_PR28 bit 0 = 1: the
TSiF control bit (FRM_PR28 bit 1) is transmitted in
bit 1 of all FAS frames and the TSiNF control bit
(FRM_PR28 bit 2) is transmitted in bit 1 of all NOT
FAS frames.
The CHI system interface (CEPT with no CRC-4 and
FRM_PR28 bit 0 = 0)
This option requires the received system data (RCHI-
DATA) to maintain a biframe alignment pattern where
frames containing Si bit information for the NOT FAS
frames have bit 2 of time slot 0 in the binary 1 state
followed by frames containing Si bit information for
the FAS frames that have bit 2 of time slot 0 in the
binary 0 state. This ensures the proper alignment of
the Si received system data to the transmit line Si
data. Whenever this requirement is not met by the
system, the transmit framer will enter a loss of
biframe alignment condition (indication is given in the
status registers) and then search for the pattern; in
the loss of biframe alignment state, transmitted line
data is corrupted (only when the system interface is
sourcing Sa or Si data). When the transmit framer
locates a new biframe alignment pattern, an indica-
tion is given in the status registers and the transmit
framer resumes normal operations.
*
.
Preliminary Data Sheet
Lucent Technologies Inc.
Lucent Technologies Inc.
October 2000