tfra08c13 ETC-unknow, tfra08c13 Datasheet - Page 5

• Manufacturer Part Number: tfra08c13
• Description: Tfra08c13 Octal T1/e1 Framer
• Manufacturer: ETC-unknow

Preliminary Data Sheet
October 2000
Lucent Technologies Inc.
Figures
Figure 29. 20-Stage Shift Register Used to Generate the Quasi-Random Signal ..................................................78
Figure 30. 15-Stage Shift Register Used to Generate the Pseudorandom Signal ..................................................79
Figure 31. TFRA08C13 Facility Data Link Access Timing of the Transmit and Receive Framer Sections ..............84
Figure 32. Block Diagram for the Receive Facility Data Link Interface....................................................................85
Figure 33. Block Diagram for the Transmit Facility Data Link Interface ...................................................................90
Figure 34. Local Loopback Mode ............................................................................................................................95
Figure 35. Remote Loopback Mode ........................................................................................................................96
Figure 36. TFRA08C13 Phase Detector Circuitry ...................................................................................................97
Figure 37. Nominal Concentration Highway Interface Timing (for FRM_PR43 bit 0—bit 2 = 100 (Binary)) ..........101
Figure 38. CHIDTS Mode Concentration Highway Interface Timing .....................................................................102
Figure 39. Associated Signaling Mode Concentration Highway Interface Timing .................................................103
Figure 40. CHI Timing with ASM and CHIDTS Enabled .......................................................................................103
Figure 41. TCHIDATA and RCHIDATA to CHICK Relationship with CMS = 0
Figure 42. Receive CHI (RCHIDATA) Timing.........................................................................................................105
Figure 43. Transmit CHI (TCHIDATA) Timing ........................................................................................................105
Figure 44. Block Diagram of the TFRA08C13's Boundary-Scan Test Logic .........................................................106
Figure 45. BS TAP Controller State Diagram ........................................................................................................107
Figure 46. Mode 1—Read Cycle Timing (MPMODE = 0) .....................................................................................116
Figure 47. Mode 1—Write Cycle Timing (MPMODE = 0)......................................................................................116
Figure 48. Mode 3—Read Cycle Timing (MPMODE = 1) .....................................................................................117
Figure 49. Mode 3—Write Cycle Timing (MPMODE = 1)......................................................................................117
Tables
Table 1. Pin Assignments for 352-Pin PBGA by Pin Number Order.......................................................................16
Table 2. Pin Descriptions........................................................................................................................................18
Table 3. AMI Encoding ...........................................................................................................................................31
Table 4. DS1 ZCS Encoding...................................................................................................................................32
Table 5. DS1 B8ZS Encoding.................................................................................................................................32
Table 6. ITUHDB3 Coding ......................................................................................................................................33
Table 7. T-Carrier Hierarchy....................................................................................................................................34
Table 8. D4 Superframe Format .............................................................................................................................36
Table 9. DDS Channel-24 Format ..........................................................................................................................37
Table 10. SLC -96 Data Link Block Format .............................................................................................................38
Table 11. SLC -96 Line Switch Message Codes .....................................................................................................39
Table 12. Transmit and Receive SLC -96 Stack Structure.......................................................................................39
Table 13. Extended Superframe (ESF) Structure...................................................................................................40
Table 14. T1 Loss of Frame Alignment Criteria ......................................................................................................41
Table 15. T1 Frame Alignment Procedures ............................................................................................................42
Table 16. Robbed-Bit Signaling Options.................................................................................................................43
Table 17. SLC -96 9-State Signaling Format ...........................................................................................................43
Table 18.16-State Signaling Format .......................................................................................................................44
Table 19. Allocation of Bits 1 to 8 of the FAS Frame and the NOT FAS Frame ......................................................46
Table 20. ITU CRC-4 Multiframe Structure.............................................................................................................49
Table 21. ITU CEPT Time Slot 16 Channel Associated Signaling Multiframe Structure ........................................55
Table 22. Transmit and Receive Sa Stack Structure...............................................................................................59
Table 23. Associated Signaling Mode CHI 2-Byte Time-Slot Format for DS1 Frames ...........................................62
Table 24. Associated Signaling Mode CHI 2-Byte Time-Slot Format for Stuffed Channels....................................62
(CEX = 3 and CER = 4, Respectively) ...............................................................................................................104
Table of Contents
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TFRA08C13 OCTAL T1/E1 Framer
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