th50vsf3582 TOSHIBA Semiconductor CORPORATION, th50vsf3582 Datasheet

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th50vsf3582

Manufacturer Part Number
th50vsf3582
Description
Sram And Flash Memory Mixed Multi-chip Package
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
TENTATIVE
SRAM AND FLASH MEMORY MIXED MULTI-CHIP PACKAGE
DESCRIPTION
33,554,432-bit flash memory. The CIOS and CIOF inputs can be used to select the optimal memory configuration.
The power supply. FLASH MEMORY a Simultaneous Read/Write operation so that data can be read during a Write
or Erase operation. The TH50VSF3582/3583AASB can range from 2.67 V to 3.3 V. The TH50VSF3582/3583AASB is
available in a 69-pin BGA package, making it suitable for a variety of design applications.
FEATURES
PIN ASSIGNMENT
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
The TH50VSF3582/3583AASB is a mixed multi-chip package containing a 8,388,608-bit Full CMOS SRAM and a
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the
buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and
to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or
damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the
most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling
Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy
control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer’s own risk.
C
D
G
H
M
Power supply voltage
Data retention supply voltage
Current consumption
Block erase architecture for flash memory
Organization
Case: CIOF = V
A
B
E
F
K
L
J
CIOF
V
V
V
CC
CC
SS
V
V
V
Operating: 45 mA maximum (CMOS level)
Standby:
Standby:
8 × 8 Kbytes
63 × 64 Kbytes
CCs
CCf
CCs
NC
NC
NC
NC
NC
NC
NC
1
CIOS
V
V
V
= 2.67 V~3.3 V
= 2.67 V~3.3 V
= 1.5 V~3.3 V
CC
SS
SS
CE
CEF
A3
A2
A1
A0
2
1
S
2,097,152 words of 16 bits
2,097,152 words of 16 bits
4,194,304 words of 8 bits
10 µA maximum (SRAM CMOS level)
10 µA maximum (FLASH)
CC
TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS
DQ0
DQ8
V
OE
, CIOS = V
A7
A6
A5
A4
3
SS
Flash Memory
DQ10
DQ1
DQ9
DQ2
A18
A17
UB
LB
(TOP VIEW)
4
CC
WP
RESET
RY
DQ11
V
DQ3
(×16, ×16)
CCf
/ACC
5
/
BY
CE2S
V
CIOS
DQ4
WE
A20
524,288 words of 16 bits
1,048,576 words of 8 bits
1,048,576 words of 8 bits
CCs
6
DQ13 DQ15 CIOF
DQ12
DQ6
DQ5
A19
A10
A8
A9
7
SRAM
DQ14
DQ7
A11
A12
A13
A14
DU
8
V
A15
A16
NC
NC
9
SS
NC
NC
NC
NC
NC
NC
10
Function mode control for flash memory
Flash memory functions
Erase and Program cycle for flash memory
Boot block architecture for flash memory
Package
PIN NAMES
Compatible with JEDEC-standard commands
Simultaneous Read/Write operations
Auto-Program
Auto Chip Erase, Auto Block Erase
Auto Multiple-Block Erase
Program Suspend/Resume
Block-Erase Suspend/Resume
Data Polling/Toggle Bit function
Block Protection/Boot Block Protection
Automatic Sleep, Hidden ROM Area Supports
Common Flash Memory Interface (CFI)
Byte/Word Mode
10
TH50VSF3582AASB: Top boot block
TH50VSF3583AASB: Bottom boot block
P-FBGA69-1209-0.80A3: 0.31 g (typ.)
CE
DQ0~DQ15
5
LB , UB
WP
A0~A21
RESET
1
RY
cycles (typical)
V
A12S
A12F
CIOS
CIOF
S
V
CEF
V
WE
OE
NC
DU
SA
CCs
CCf
/ACC
SS
/
, CE2S Chip Enable Inputs for SRAM
BY
TH50VSF3582/3583AASB
Address Inputs
A12 Input for SRAM
A12 Input for Flash Memory
A18 Input for SRAM
Data Inputs/Outputs
Chip Enable Input for Flash Memory
Output Enable Input
Write Enable Input
Data Byte Control Input
Ready/Busy Output
Hardware Reset Input
Write Protect/Program Acceleration Input
Word Enable Input for SRAM
Word Enable Input for Flash Memory
Power Supply for SRAM
Power Supply for Flash Memory
Ground
Not Connected
Don’t Use
2001-06-08 1/50
000707EBA2

Related parts for th50vsf3582

th50vsf3582 Summary of contents

Page 1

... The CIOS and CIOF inputs can be used to select the optimal memory configuration. The power supply. FLASH MEMORY a Simultaneous Read/Write operation so that data can be read during a Write or Erase operation. The TH50VSF3582/3583AASB can range from 2. 3.3 V. The TH50VSF3582/3583AASB is available in a 69-pin BGA package, making it suitable for a variety of design applications. ...

Page 2

... A16 NC DQ4 DQ13 DQ15 CIOF V DQ12 DQ7 V CCs SS CIOS DQ5 DQ14 A11 CE2S A20 A13 A16 A21 A9 A14 NC A10 A15 NC NC DQ6 A12S A17 NC DQ4 DU A12F CIOF V DU DQ7 V CCs SS CIOS DQ5 TH50VSF3582/3583AASB 000707EBA2 2001-06-08 2/50 ...

Page 3

... Word Mode is selected for both SRAM and flash memory and CE2S = V at the same time TH50VSF3582/3583AASB DQ0~DQ15 (DQ0~DQ7) DQ0~DQ15 DQ0~DQ15 (DQ0~DQ7 /ACC DQ0~DQ7 DQ8~DQ15 OUT OUT OUT ...

Page 4

... TYPE Manufacturer Code TH50VSF3582AASB Device Code TH50VSF3583AASB Verify Block Protect Note (1) DQ8~DQ15 are Hi-Z in Byte mode (2) BA: Block address (3) 0001H: Protected block 0000H: Unprotected block TH50VSF3582/3583AASB A20~A12 ( (1) A0 CODE (HEX) ...

Page 5

... IA: Bank Address and ID Read Address (A6, A1, A0) Bank Address = A20~A15 Manufacturer Code = ( Device Code = ( (5) ID: ID Data 0098H - Manufacturer Code 009AH - Device Code (TH50VSF3582AASB) 009CH - Device Code (TH50VSF3583AASB) 0001H - Protected Block SECOND BUS THIRD BUS FOURTH BUS WRITE CYCLE ...

Page 6

... BLOCK ERASE ADDRESS TABLES TH50VSF3582AASB (top boot block) BANK BLOCK BANK ADDRESS # # A20 A19 A18 A17 A16 A15 A14 A13 A12 BA0 L L BA1 L L BA2 L L BA3 L L BK0 BA4 L L BA5 L L BA6 L L BA7 L L BA8 L L BA9 ...

Page 7

... H L BK6 BA52 BA53 BA54 BA55 BA56 BA57 BA58 BK7 BA59 BA60 BA61 BA62 TH50VSF3582/3583AASB BYTE MODE 200000H~20FFFFH * * * 210000H~21FFFFH * * * 220000H~22FFFFH * * * 230000H~23FFFFH * * * 240000H~24FFFFH 250000H~25FFFFH ...

Page 8

... A20 A19 A18 A17 A16 A15 A14 A13 A12 BA63 BA64 BA65 BA66 BK8 BA67 BA68 BA69 BA70 TH50VSF3582/3583AASB BYTE MODE 3F0000H~3F1FFFH 3F2000H~3F3FFFH 3F4000H~3F5FFFH 3F6000H~3F7FFFH ...

Page 9

... L H BA23 BA24 BA25 BA26 BK3 BA27 BA28 BA29 BA30 TH50VSF3582/3583AASB BLOCK ADDRESS BYTE MODE 000000H~001FFFH 002000H~003FFFH 004000H~005FFFH 006000H~007FFFH ...

Page 10

... BA52 BA53 BA54 BA55 BA56 BA57 BA58 BK7 BA59 BA60 BA61 BA62 TH50VSF3582/3583AASB BYTE MODE 180000H~18FFFFH * * * 190000H~19FFFFH * * * 1A0000H~1AFFFFH * * * 1B0000H~1BFFFFH * * * 1C0000H~1CFFFFH 1D0000H~1DFFFFH ...

Page 11

... BANK ADDRESS # # A20 A19 A18 A17 A16 A15 A14 A13 A12 BA63 BA64 BA65 BA66 BK8 BA67 BA68 BA69 BA70 TH50VSF3582/3583AASB BYTE MODE 380000H~38FFFFH * * * 390000H~39FFFFH * * * 3A0000H~3AFFFFH * * * 3B0000H~3BFFFFH * * * 3C0000H~3CFFFFH ...

Page 12

... BLOCK SIZE TABLE TH50VSF3582AASB (top boot block) BLOCK SIZE BLOCK # BYTE MODE WORD MODE BA0~BA7 64 Kbytes 32 Kwords BA8~BA15 64 Kbytes 32 Kwords BA16~BA23 64 Kbytes 32 Kwords BA24~BA31 64 Kbytes 32 Kwords BA32~BA39 64 Kbytes 32 Kwords BA40~BA47 64 Kbytes 32 Kwords BA48~BA55 64 Kbytes 32 Kwords BA56~BA62 64 Kbytes 32 Kwords BA63~BA70 8 Kbytes TH50VSF3583AASB (bottom boot block) ...

Page 13

... Output when the block address selected for Auto Block Erase is specified and data is read from there. During Auto Chip Erase, all blocks are selected. (3) Output when a block address not selected for Auto Block Erase of same bank as selected block is specified and data is read from there. TH50VSF3582/3583AASB −0.5~V (2) DQ7 ...

Page 14

... V for pulse width ≤ CAPACITANCE ( 25° MHz) SYMBOL PARAMETER C Input Capacitance IN C Output Capacitance OUT Note: These parameters are sampled periodically and are not tested for every device. TH50VSF3582/3583AASB ( -30°~85°C) MIN TYP. 2.67  2.2  (1) −0.3  1.5  ...

Page 15

... High Voltage Input Current for I ACC WP /ACC (1) The device is going to Automatic Sleep Mode, when address remain steady during 150 ns. (2) In Standby Mode, with ≥ V CCs CIOS ≥ V − 0 CIOS ≤ 0.2 V. CCs TH50VSF3582/3583AASB / 2.67 V~3.3 V) CCs CCf CONDITION V ≤ V ≤ − ...

Page 16

... Data Set-up Time DS t Data Hold Time DH AC TEST CONDITIONS PARAMETER Input Pulse Level Input Pulse Rise and Fall Time (10%~90%) Timing Measurement Reference Level (input) Timing Measurement Reference Level (output) Output Load TH50VSF3582/3583AASB = = = = 2.7 V~3.6 V) CCs PARAMETER PARAMETER C (100 pF TTL gate L MIN MAX UNIT 70  ...

Page 17

... WE Low-Level Hold Time PPLH PROGRAM AND ERASE CHARACTERISTICS SYMBOL Auto-Program Time (Byte Mode) t PPW Auto-Program Time (Word Mode) t Auto Chip Erase Time PCEW t Auto Block Erase Time PBEW t Erase/Program Cycle EW *: typ. TH50VSF3582/3583AASB LOAD CAPACITANCE 30pF MIN MAX 70  70  70  30  0  0  0  ...

Page 18

... CEF Set-up time BYTE Transition CEBTS t Program Suspend Command to Suspend Mode SUSP t Program Resume Command to Program Mode RESP t Erase Suspend Command to Suspend Mode SUSE t Erase Resume Command to Erase Mode RESE TH50VSF3582/3583AASB LOAD CAPACITANCE 30pF MIN Control Control) 20 ...

Page 19

... The TH50VSF3582/3583AASB has a total of nine banks: 0.5 Mbits × 1 bank, 3.5 Mbits × 1 bank, and 4 Mbits × 7 banks. Banks are switched using bank addresses (A20 to A15). For bank blocks and addresses, refer to the Block Address Table and Block Size Table ...

Page 20

... Sleep mode is automatically released, outputting data from the changed address. Output Disable Mode Inputting disables output from the device, setting DQ to high-impedance. IH TH50VSF3582/3583AASB ± 0 CEF and RESET . The device enters Standby DD ). However, if the device is in simultaneous operation, CCS1 ± ...

Page 21

... BYTE /WORD Mode CIOF is used select Word mode (16 bits) or Byte mode (8 bits) for the TH50VSF3582/3583AASB. When V input to CIOF, the device operates in Word mode. Read data or write commands using DQ0 to DQ15. When V is input to CIOF, read data or write commands using DQ0 to DQ7. A12F is used as the lowest address. DQ8 to DQ14 become high-impedance ...

Page 22

... Auto-Program Mode The TH50VSF3582/3583AASB can be programmed in either byte or word units. The Auto Program mode is set using the Program command. The program address is latched on the falling edge of the WE signal and data is latched on the rising edge of the fourth bus cycle (with WE control). Auto programming starts on the rising edge of the WE signal in the fourth bus cycle ...

Page 23

... In this case, the block in which a failure occurred cannot be detected. Either terminate device usage, or perform Block Erase for each block, specify the failed block, and stop using it. The host processor must take measures to prevent use of the failed block being used in the future. TH50VSF3582/3583AASB . SUSP ...

Page 24

... Erase Hold Time, the device will return to the state it was in at the start of the Erase Hold Time. At this time more blocks can be specified for erasing Erase Resume command is input during an Auto Block Erase, Erase resumes. At this time toggle output of DQ6 resumes and 0 is output TH50VSF3582/3583AASB . The SUSE 2001-06-08 24/50 th ...

Page 25

... The target blocks are two of the boot blocks. The Top Boot Block uses BA69/BA70; the Bottom Boot Block, BA0/BA1. Inputting block protection mode. TH50VSF3582/3583AASB and are input. At this time, the device writes to the block IL but the device need not be controlled PPLH to the RESET pin ...

Page 26

... Hidden Rom Area The TH50VSF3582/3583AASB features a 64-Kbyte Hidden ROM area apart from the memory cells. The area consists of one block. Data Read, Write, and Protect can be performed on the block. Because Protect cannot be released, once the block is protected, data in the block cannot be overwritten. ...

Page 27

... Common Flash Memory Interface (CFI) The TH50VSF3582/3583AASB conforms to the CFI. Information on device specifications and characteristics can be obtained via CFI. To read information from the device, input the Query command followed by the address. In Word mode, DQ8 to DQ15 all output 0s. To exit this mode, input the Reset command. ...

Page 28

... Block Protect/Unprotect scheme Simultaneous Operation 0: Not Supported 1: Supported Burst Mode 0: Not Supported Page Mode 0: Not Supported V Min voltage ACC DQ7~DQ4 DQ3~DQ0: 100 mV V Max voltage ACC DQ7~DQ4 DQ3~DQ0: 100 mV Top/Bottom Boot Block Flag 2: TH50VSF3582AASB 3: TH50VSF3583AASB Program Suspend 0: Not Supported 1: Supported 2001-06-08 28/50 ...

Page 29

... HARDWARE SEQUENCE FLAGS FOR FLASH MEMORY The TH50VSF3582/3583AASB has a Hardware Sequence flag which allows the device status to be determined during an auto mode operation. The output data is read out using the same timing as that used when CEF = Read Mode. The output can be either High or Low ...

Page 30

... DQ2 outputs BUSY (READY / ) The TH50VSF3582/3583AASB has a (Busy state) indicates that an Auto Program or Auto Erase operation is in progress (Ready state) indicates that the operation has finished and that the device can accept a new command. The when an operation has failed. The signal outputs a 0 after the rising edge the last command cycle ...

Page 31

... DATA PROTECTION The TH50VSF3582/3583AASB features a function which makes malfunction or data damage difficult. Protection Against Program/Erase Caused by Low Supply Voltage To prevent malfunction at power on or power down, the device does not receive commands when this state, command input is ignored. LKO If V drops below V during Auto operations, the device terminates Auto Program execution ...

Page 32

... SRAM READ CYCLE (see Note 1) Address CE2S Hi-Z OUT Data Invalid ACC OEE t CEE Hi ACC t CO2 t CO1 OEE t COE Valid Data Out t COE TH50VSF3582/3583AASB DF1 t DF2 Valid Data Out Hi ODO t BD Hi-Z 2001-06-08 32/50 ...

Page 33

... See Note 2 OUT D See Note SRAM WRITE CYCLE 2 ( -CONTROLLED) (see Note 4) Address CE2S Hi-Z OUT D See Note 5 IN TH50VSF3582/3583AASB ODW OEW Hi Valid Data ...

Page 34

... CE2S Hi-Z OUT D See Note SRAM WRITE CYCLE and Address CE2S Hi-Z OUT D See Note 5 IN TH50VSF3582/3583AASB ODW t COE Valid Data In LB -CONTROLLED) (see Note ...

Page 35

... This is the timing of the Command Write Operation. The timing which described follow pages is typically same as this page’s. WE Control • Address t AS CEF CEF Control • Address t AS CEF TH50VSF3582/3583AASB t CMD Command Address AHW t t CES CEH t t WELH WEHH ...

Page 36

... Read Mode (Input ID Read Command Sequence) (Continued) Address 555H t CMD CEF AAH IN D OUT ID Read Mode (input of Reset command sequence) Notes: Word mode address shown BK: Bank address TH50VSF3582/3583AASB 2AAH BK + 555H BK + 00H t RC 55H 90H Manufacturer Code Hi-Z ID Read Mode 2AAH 555H F0H 55H Hi-Z Read Mode ...

Page 37

... FLASH AUTO CHIP ERASE/AUTO BLOCK ERASE OPERATION ( 555H 2AAH Address t CMD CEF OE t OES WE D AAH IN t VCS V CCf Notes: Word mode address shown BA: Block address for Auto Block Erase operation TH50VSF3582/3583AASB WE -CONTROLLED) 2AAH 555H PA 55H A0H PD Hi-Z 555H 555H 55H 80H AAH PA t OEHP t PPW ...

Page 38

... FLASH AUTO CHIP ERASE/AUTO BLOCK ERASE OPERATION ( Address 555H 2AAH t CMD CEF OE t OES WE D AAH IN t VCS V CCf Note: Word Mode address shown. BA: Block address for Auto Block Erase operation TH50VSF3582/3583AASB CEF -CONTROLLED) 555H PA 55H A0H PD Hi-Z 555H 555H 55H 80H AAH PA t PPW t OEHP D ...

Page 39

... CEF OE t OES WE t DF1 t DF2 OUT OUT Suspend Mode PA: Program address BK: Bank address BA: Block address RA: Read address Flag: Hardware Sequence flag TH50VSF3582/3583AASB OUT /t SUSE Suspend Mode RESP RESE 30H Hi-Z Program/Erase Mode Hi-Z PA/ ...

Page 40

... FLASH DURING AUTO-PROGRAM/ERASE OPERATION CEF FLASH HARDWARE RESET OPERATION WE RESET RESET FLASH READ AFTER Address RESET D Hi-Z OUT TH50VSF3582/3583AASB Command input sequence During operation t BUSY READY ACC Valid Data Out t OH 2001-06-08 40/50 ...

Page 41

... Address Command Address t CMD CEF OE t OEHP WE Last D Command IN Data DQ2/DQ6 t BUSY PA: Program address BA: Block address *DQ2/DQ6 stops toggling when auto operation has been completed. TH50VSF3582/3583AASB DATA Polling) PA/ PPW PCEW PBEW ACC DQ 7 Valid Invalid Valid PA/BA t ...

Page 42

... FLASH BLOCK PROTECT OPERATION Address t CMD CEF VPS RESET D 60h IN D OUT Notes Block address Next Block address * : 01h indicates that block is protected. TH50VSF3582/3583AASB CMD CMD t PPLH 60h 40h 60h 01h* 2001-06-08 42/50 ...

Page 43

... High during a Write cycle, the outputs will remain High-Impedance. (5) Because I/O pins may be in Output state at this point, input signals of the opposite value must not be applied. ( stops toggling when the last command has been completed. OUT TH50VSF3582/3583AASB t t CCR CCR 2001-06-08 43/50 ...

Page 44

... CE2S ≤ 0 CE2S ≥ V CCs (2) When operating at the V transition of V from 2. 2.3 V. CCs (3) In CE2S-Controlled Data Retention Mode, Minimum Standby Current Mode is entered when CE2S ≤ 0.2 V. TH50VSF3582/3583AASB ( -30°~85°C) MIN 1 3 −30°~85°C  −30°~40°C  3 − ...

Page 45

... FLOWCHARTS OF FLASH MEMORY OPERATIONS Auto-Program Address = Address + 1 Note: Word mode command sequence is shown. TH50VSF3582/3583AASB Start Auto-Program Command Sequence (see below) DATA Polling or Toggle Bit No Last Address? Yes Auto-Program Completed Auto-Program command sequence (address/data) 555H/AAH 2AAH/55H 555H/A0H Program address/program data 2001-06-08 45/50 ...

Page 46

... Fast Program Address = Address + 1 Fast Program Set command sequence (address/data) 555H/AAH 2AAH/55H 555H/20H TH50VSF3582/3583AASB Start Fast Program Set Command Sequence (see below) Fast Program Command Sequence (see below) DATA Polling or Toggle Bit No Last Address? Yes Program Sequence (see below) Fast Program ...

Page 47

... Auto-Erase Command Sequence Auto Chip Erase command sequence (address/data) 555H/AAH 2AAH/55H 555H/80H 555H/AAH 2AAH/55H 555H/10H Note: Word mode command sequence is shown. TH50VSF3582/3583AASB Start (see below) DATA Polling or Toggle Bit Auto-Erase Completed Auto Block Erase / Multiple-Block Erase command sequence (address/data) 555H/AAH 2AAH/55H ...

Page 48

... VA: Byte address for programming. Any of the addresses within the block being erased during a Block Erase operation. Don’t care during a Chip Erase operation. Any address not within the current block during an Erase Suspend operation. TH50VSF3582/3583AASB Yes DQ7 must be rechecked even if DQ5 = 1 because DQ7 may change at the same time as DQ5 ...

Page 49

... Verify Block Protect Data = 01h? Yes Protect Another Block? Remove V ID Reset Command Block Protect Complete BPA: Block Address and ID Read Address (A6, A1, A0) ID Read Address = ( TH50VSF3582/3583AASB ID PLSCNT = PLSCNT + 1 No PLSCNT = 25? Yes Remove V No from RESET Reset Command Device Failed ...

Page 50

... PACKAGE DIMENSIONS TH50VSF3582/3583AASB Unit: mm 2001-06-08 50/50 ...

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