am49lv128bm Meet Spansion Inc., am49lv128bm Datasheet - Page 12

• Manufacturer Part Number: am49lv128bm
• Description: Stacked Multi-chip Package Mcp ,128 Megabit 8 M ? 16-bit ,uniform Sector Flash Memory And 32 Mbit 2 M ? 16-bit Pseudo-static Ram With Page Mode Featuring Mirrorbit Technology,supplemental Datasheet
• Manufacturer: Meet Spansion Inc.

DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
Legend: L = Logic Low = V
Address, A
Notes:
1. Addresses are A22:A0. Sector addresses are A22:A15 in both modes.
2. The sector group protect and sector group unprotect functions may also be implemented via programming equipment. See the
3. If WP# = V
4. D
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
10
Read
Write (Program/Erase)
Accelerated Program
Standby
Output Disable
Reset
Sector Group Protect
(Note 2)
Sector Group Unprotect
(Note 2)
Temporary Sector Group
Unprotect
“Sector Group Protection and Unprotection” section.
determined by the method described in “Write Protect (WP#)”. All sectors are unprotected when shipped from the factory (The
SecSi Sector may be factory protected depending on version ordered.)
IN
or D
Operation
IN
OUT
= Address In, D
IL
, the first or last sector remains protected. If WP# = V
as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
IH
.
IL
, H = Logic High = V
IN
V
0.3 V
CE#
CC
X
X
= Data In, D
L
L
L
L
L
L
±
IL
OE#
. CE# is the power
H
H
H
H
H
X
X
X
L
OUT
Table 1. Device Bus Operations
WE#
H
H
L
L
X
X
L
L
X
= Data Out
IH
, V
ID
RESET#
Am49LV128BM
V
0.3 V
= 11.5–12.5 V, V
V
V
V
CC
H
H
H
H
L
ID
ID
ID
±
IH
(Note 3)
(Note 3)
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read-Only Operations table for timing spec-
ifications and to Figure 14 for the timing diagram.
Refer to the DC Characteristics table for the active
current specification on reading array data.
, the first or last sector will be protected or unprotected as
WP#
X
X
X
X
H
H
H
HH
= 11.5–12.5 V, X = Don’t Care, SA = Sector
ACC
V
X
X
H
X
X
X
X
X
HH
A3=L, A2=L,
A3=L, A2=L,
A1=H, A0=L
A1=H, A0=L
Addresses
SA, A6 =L,
SA, A6=H,
(Note 2)
A
A
A
A
X
X
X
IN
IN
IN
IN
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
High-Z
High-Z
High-Z
DQ0–
D
DQ7
OUT
June 17, 2004
(Note 4)
(Note 4)
(Note 4)
High-Z
High-Z
High-Z
DQ8–
DQ15
D
OUT
X
X