am49lv128bm Meet Spansion Inc., am49lv128bm Datasheet - Page 88

• Manufacturer Part Number: am49lv128bm
• Description: Stacked Multi-chip Package Mcp ,128 Megabit 8 M ? 16-bit ,uniform Sector Flash Memory And 32 Mbit 2 M ? 16-bit Pseudo-static Ram With Page Mode Featuring Mirrorbit Technology,supplemental Datasheet
• Manufacturer: Meet Spansion Inc.

TIMING WAVEFORM OF PAGE MODE WRITE CYCLE
POWER SAVINGS MODES
The PSRAM has three power savings modes:
The operation of the power saving modes is controlled
by setting the Variable Address Register (VAR). This
VAR is used to enable/disable the various low power
modes.
The VAR is set by using the timings. The register must
be set in less then 1µs after ZZ# is enabled low.
Reduced Memory Size (RMS)
In this mode of operation, the 32Mb PSRAM can be
operated as a 8Mb, 16Mb or a 24Mb device. The
mode and array size are determined by the settings in
the VA register. The VA register is set according to the
timings and the bit settings. The RMS mode is enabled
at the time of ZZ# transitioning high and the mode re-
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Reduced Memory Size
Partial Array Refresh
Deep Sleep Mode
Am49LV128BM
mains active until the register is updated. To return to
the full 32Mb address space, the VA register must be
reset using the previously defined procedures.
Partial Array Refresh (PAR)
In this mode, the internal refresh operation can be re-
stricted to a 8Mb, 16Mb or 24Mb portion of the array.
The mode and array partition to be refreshed are de-
termined by the settings in the VAR register. The VAR
register is set according to the timings and the bit set-
tings. In this mode, when ZZ# is taken low, only the
portion of the array that is set in the register is re-
freshed. The operating mode is only available during
standby time and once ZZ# is returned high, the de-
vice resumes full array refresh. All future PAR cycles
will use the contents of the VA register. To change the
address space of the PAR mode, the VA register must
be reset using the previously defined procedures.
The default state for the ZZ# register will be such that
ZZ# low will put the device into PAR mode after 1µs
and never initiate a deep sleep mode unless appropri-
June 17, 2004