am49lv128bm Meet Spansion Inc., am49lv128bm Datasheet - Page 14

• Manufacturer Part Number: am49lv128bm
• Description: Stacked Multi-chip Package Mcp ,128 Megabit 8 M ? 16-bit ,uniform Sector Flash Memory And 32 Mbit 2 M ? 16-bit Pseudo-static Ram With Page Mode Featuring Mirrorbit Technology,supplemental Datasheet
• Manufacturer: Meet Spansion Inc.

RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all output pins, and ignores all read/
write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to
reading array data. The operation that was interrupted
should be reinitiated once the device is ready to ac-
cept another command sequence, to ensure data in-
tegrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
held at V
rent will be greater.
12
Sector
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
IL
but not within V
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SS
±0.3 V, the standby cur-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SS
CC4
±0.3 V, the device
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
A22–A15
). If RESET# is
Table 2. Sector Address Table
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
RP
Am49LV128BM
, the
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 16 for the timing diagram.
V
The device imposes no restrictions on V
or power-down sequencing. Asserting RESET# to VIL
is required during the entire V
the respective supplies reach their operating voltages.
Once V
RESET# to V
Output Disable Mode
When the OE# input is at V
is disabled. The output pins are placed in the high
impedance state.
CC
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Power-up and Power-down Sequencing
CC
attains its operating voltage, de-assertion of
IH
Sector Size
(Kwords)
is permitted.
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
IH
CC
, output from the device
power sequence until
(in hexadecimal)
0A8000–0AFFFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0A0000–0A7FFF
0B0000–0B7FFF
0E0000–0E7FFF
Address Range
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
16-bit
June 17, 2004
CC
power-up