am49lv128bm Meet Spansion Inc., am49lv128bm Datasheet - Page 6

• Manufacturer Part Number: am49lv128bm
• Description: Stacked Multi-chip Package Mcp ,128 Megabit 8 M ? 16-bit ,uniform Sector Flash Memory And 32 Mbit 2 M ? 16-bit Pseudo-static Ram With Page Mode Featuring Mirrorbit Technology,supplemental Datasheet
• Manufacturer: Meet Spansion Inc.

AM49LV128BM MCP With Second PSRAM
Supplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
pSRAM Block Diagram . . . . . . . . . . . . . . . . . . . . . 76
Absolute Maximum Ratings (Note 1) . . . . . . . . . .76
4
Read TIming #1 (Basic Timing) . . . . . . . . . . 63
Read Timing #2 (OE# and Address Access) . . 64
Read Timing #3 (LB#/UB# Byte Access) . . . . 65
Read Timing #4 (Page Access after CE1#
Control Access) . . . . . . . . . . . . . . . . . . . . . 65
Read Timing #5 (Random and Page Address
Access) . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Write Timing #1 (Basic Timing) . . . . . . . . . . 67
Write Timing #2 (WE# Control) . . . . . . . . . . 67
Write Timing #3-1 (WE#/LB#/UB# Byte Write
Control) . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Write Timing #3-2 (WE#/LB#/UB# Byte Write
Control) . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Write Timing #3-3 (WE#/LB#/UB# Byte Write
Control) . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Write Timing #3-4 (WE#/LB#/UB# Byte Write
Control) . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Read/Write Timing #1-1 (CE1# Control) . . . 71
Read/Write Timing #1-2 (CE1#/WE#/OE#
Control) . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Read/Write Timing #2 (OE#, WE# Control) . 72
Read/Write Timing #3 (OE#, WE#, LB#, UB#
Control) . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Power-up Timing #1 . . . . . . . . . . . . . . . . . 73
Power-up Timing #2 . . . . . . . . . . . . . . . . . 73
Power-down Entry and Exit Timing. . . . . . . . 74
Standby Entry Timing after Read or Write . . . 74
Am49LV128BM
Operating Characteristics (Over Specified
Temperature Range) . . . . . . . . . . . . . . . . . . . . . . . 77
Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . 78
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Timing of Read Cycle (CE# = OE# = V
WE# = V
Timing Waveform of Read Cycle (WE#=V
Timing Waveform of Page Mode Read Cycle
(WE# = V
Timing Waveform of Write Cycle
(WE# Control). . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Timing Waveform of Write Cycle
(CE# Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Timing Waveform for Successive WE# Write
Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Timing Waveform of Page Mode Write Cycle. . 86
Variable Address Register . . . . . . . . . . . . . . . . . . 88
Variable Address Register (VAR) Update
Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Deep Sleep Mode - Entry/Exit Timings . . . . . . . . 90
Address Patterns for PAR (A3 = 0, A4 = 1) . . . . . . 91
Address Patterns for RMS (A3 = 1, A4 = 1) . . . . . 92
Low Power ICC Characteristics for PSRAM . . . . 93
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 94
Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . 95
Reduced Memory Size (RMS) . . . . . . . . . 86
Partial Array Refresh (PAR) . . . . . . . . . . . 86
Deep Sleep Mode . . . . . . . . . . . . . . . . . . 87
TLD064–64-Ball Fine-pitch Ball Grid Array ............................. 94
IH
IH
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
June 17, 2004
IL
,
IH
) . . . 81