mt18lsdf6472y-133 Micron Semiconductor Products, mt18lsdf6472y-133 Datasheet - Page 11

• Manufacturer Part Number: mt18lsdf6472y-133
• Description: 512mb X72, Ecc, Sr 168-pin Sdram Rdimm
• Manufacturer: Micron Semiconductor Products

Figure 5:
CAS Latency
Operating Mode
Write Burst Mode
PDF: 09005aef80a2e32f/Source: 09005aef80d04a5a
SDF18C64x72G.fm - Rev. E 9/05 EN
CAS Latency Diagram
CL is the delay, in clock cycles, between the registration of a READ command and the
availability of the first piece of output data. The latency can be set to two or three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. DQ will start driving as a result of the clock edge
one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data
will be valid by clock edge n + m. For example, assuming that the clock cycle time is such
that all relevant access times are met, if a read command is registered at T0 and the
latency is programmed to two clocks, DQ will start driving after T1 and the data will be
valid by T2, as shown in Figure 5. Table 6 on page 12, indicates the operating frequencies
at which each CL setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-
nations of values for M7 and M8 are reserved for future use and/or test modes. The pro-
grammed BL applies to both read and write bursts.
Test modes and reserved states should not be used because unknown operation or
incompatibility with future versions may result.
When M9 = 0, the BL programmed via M0–M2 applies to both read and write bursts;
when M9 = 1, the programmed BL applies to read bursts, but write accesses are single-
location (nonburst) accesses.
COMMAND
COMMAND
CLK
CLK
DQ
DQ
READ
READ
T0
T0
CAS Latency = 2
NOP
NOP
T1
T1
t
t AC
LZ
CAS Latency = 3
512MB (x72, ECC, SR): 168-PIN SDRAM RDIMM
11
T2
NOP
T2
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t AC
LZ
D
t OH
OUT
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
Mode Register Definition
T4
©2001 Micron Technology, Inc. All rights reserved.