mt18lsdf6472y-133 Micron Semiconductor Products, mt18lsdf6472y-133 Datasheet - Page 12

• Manufacturer Part Number: mt18lsdf6472y-133
• Description: 512mb X72, Ecc, Sr 168-pin Sdram Rdimm
• Manufacturer: Micron Semiconductor Products

Figure 6:
Commands
Table 7:
PDF: 09005aef80a2e32f/Source: 09005aef80d04a5a
SDF18C64x72G.fm - Rev. E 9/05 EN
Name (Function)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh
mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
Registered mode adds one clock cycle to CL
SDRAM Commands and DQMB Operation Truth Table
CKE is HIGH for all commands shown except SELF REFRESH
CAS Latency Table
Speed
-13E
-133
Notes: 1. A0–A12 provide row address; BA0–BA1 determine which device bank is made active.
Table 7, provides a quick reference of available commands. This is followed by written
description of each command. For a more detailed description of commands and opera-
tions, refer to the 256Mb SDRAM component data sheet.
2. A0–A9, A11 provide column address; A10 HIGH enables the auto-precharge feature (non-
3. A10 LOW: BA0–BA1 determine which device bank is being precharged. A10 HIGH: all
4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care”
6. A0–A11 define the op-code written to the mode register and A12 should be driven LOW.
7. Activates or deactivates DQ during WRITEs (zero-clock delay) and READs (two-clock delay).
persistent), while A10 LOW disables the auto-precharge feature; BA0–BA1 determine
which device bank is being read from or written to.
device banks are precharged and BA0, BA1 are “Don’t Care.”
except for CKE.
CL = 2
≤ 133
≤ 100
512MB (x72, ECC, SR): 168-PIN SDRAM RDIMM
CS#
12
H
L
L
L
L
L
L
L
L
–
–
RAS# CAS#
X
H
H
H
H
L
L
L
L
–
–
Clock Frequency (MHz)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Allowable Operating
X
H
H
H
H
L
L
L
L
–
–
WE# DQMB
X
H
H
H
H
L
L
L
L
–
–
L/H
L/H
X
X
X
X
X
X
X
H
L
©2001 Micron Technology, Inc. All rights reserved.
Bank/Row
Bank/Col
Bank/Col
Op-code
ADDR
CL = 3
Code
≤ 143
≤ 133
X
X
X
X
–
–
Commands
High-Z
Active
Active
Valid
DQ
X
X
X
X
X
X
X
Notes
4, 5
1
2
2
3
6
7
7