mt18lsdf6472y-133 Micron Semiconductor Products, mt18lsdf6472y-133 Datasheet - Page 7

• Manufacturer Part Number: mt18lsdf6472y-133
• Description: 512mb X72, Ecc, Sr 168-pin Sdram Rdimm
• Manufacturer: Micron Semiconductor Products

General Description
PLL and Register Operation
Serial Presence-Detect Operation
PDF: 09005aef80a2e32f/Source: 09005aef80d04a5a
SDF18C64x72G.fm - Rev. E 9/05 EN
The MT18LSDF6472 is a high-speed CMOS, dynamic random-access, 512MB memory
module organized in a x72 (ECC) configuration. This module uses internally configured
quad-bank SDRAMs with a synchronous interface (all signals are registered on the posi-
tive edge of the clock signal).
Read and write accesses to SDRAM modules are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1
select the device bank; A0–A12 select the device row). The address bits registered coinci-
dent with the READ or WRITE command are used to select the starting device column
location for the burst access.
SDRAM modules provide for programmable read or write BL of 1, 2, 4, or 8 locations, or
full page, with a burst terminate option. An auto precharge function may be enabled to
provide a self-timed row precharge that is initiated at the end of the burst sequence.
SDRAM modules use an internal pipelined architecture to achieve high-speed operation.
This architecture is compatible with the 2n rule of prefetch architectures, but it also
allows the device column address to be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one device bank while accessing one of the
other three device banks will hide the PRECHARGE cycles and provide seamless, high-
speed, random-access operation.
SDRAM modules are designed to operate in +3.3V ±0.3V, low-power memory systems.
An auto refresh mode is provided, along with a power-saving, power-down mode. All
inputs and outputs are LVTTL-compatible.
SDRAM modules offer substantial advances in DRAM operating performance, including
the ability to synchronously burst data at a high data rate with automatic column-
address generation, the ability to interleave between device banks in order to hide pre-
charge time, and the capability to randomly change device column addresses on each
clock cycle during a burst access. For more information regarding SDRAM operation,
refer to the 256Mb SDRAM component data sheet.
SDRAM modules can be operated in either registered mode (REGE pin HIGH), where the
control/address input signals are latched in the register on one rising clock edge and
sent to the SDRAM devices on the following rising clock edge (data access is delayed by
one clock), or in buffered mode (REGE pin LOW) where the input signals pass through
the register/buffer to the SDRAM devices on the same clock. A phase-lock loop (PLL) on
the modules is used to redrive the clock signals to the SDRAM devices to minimize sys-
tem clock loading (CK0 is connected to the PLL, and CK1, CK2, and CK3 are terminated).
SDRAM modules incorporate serial presence-detect (SPD). The SPD function is imple-
mented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes.
The first 128 bytes can be programmed by Micron to identify the module type and vari-
ous SDRAM organizations and timing parameters. The remaining 128 bytes of storage
are available for use by the customer. System READ/WRITE operations between the
master (system logic) and the slave EEPROM device (DIMM) occur via a standard I
512MB (x72, ECC, SR): 168-PIN SDRAM RDIMM
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2001 Micron Technology, Inc. All rights reserved.
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