mt18lsdf6472y-133 Micron Semiconductor Products, mt18lsdf6472y-133 Datasheet - Page 4

• Manufacturer Part Number: mt18lsdf6472y-133
• Description: 512mb X72, Ecc, Sr 168-pin Sdram Rdimm
• Manufacturer: Micron Semiconductor Products

Table 5:
PDF: 09005aef80a2e32f/Source: 09005aef80d04a5a
SDF18C64x72G.fm - Rev. E 9/05 EN
33–38, 117–121, 123,
2–5, 7–11, 13–17, 19,
20, 55–58, 60, 65–67,
69–82, 74–77, 86–89,
91–95, 97–101, 103,
28, 29, 46, 47, 112,
21, 22, 52, 53, 105,
104, 139–142, 144,
149–151, 153–156,
113, 130, 131
166, 167, 168
106, 136, 137
27, 111, 115
158–161
39, 122
30, 45
Pins
128
126
147
42
83
82
Pin Descriptions
Pin numbers not listed in correct order; for more information, see Pin Assignment tables on page 3
WE#, CAS#,
DQ0–DQ63
BA0, BA1
DQMB0–
SA0–SA2
CB0–CB7
Symbol
S0#, S2#
DQMB7
A0–A12
RAS#
CKE0
REGE
SDA
CK0
SCL
Output
Output
Output
Input/
Input/
Input/
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
Description
Command inputs: WE#, CAS#, and RAS# (along with S#) define the
command being entered.
Clock: CK is distributed through an on-board PLL to all devices.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CK signal.
Deactivating the clock provides POWER-DOWN and SELF REFRESH
operation (all device banks idle) or CLOCK SUSPEND operation (burst
access in progress). CKE is synchronous except after the device enters
power-down and self refresh modes, where CKE becomes asynchronous
until after exiting the same mode. The input buffers, including CKE, are
disabled during power-down and self refresh modes, providing low
standby power.
Chip select: S# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when S# is registered
HIGH. S# is considered part of the command code.
Input/Output mask: DQMB is an input mask signal for write accesses and
an output enable signal for read accesses. Input data is masked when
DQMB is sampled HIGH during a WRITE cycle. The output buffers are
placed in a High-Z state (two-clock latency) when DQMB is sampled HIGH
during a READ cycle.
Bank address: BA0 and BA1 define to which device bank the ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.
Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE
commands, to select one location out of the memory array in the
respective device bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10
LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE REGISTER
SET command. BA0 and BA1 define which mode register (mode register
or extended mode register) is loaded during the LOAD MODE REGISTER
command.
Serial clock for presence-detect: SCL is used to synchronize the presence-
detect data transfer to and from the module.
Presence-Detect address inputs: These pins are used to configure the
presence-detect device.
Register enable.
Data I/Os: Data bus.
ECC check bits.
Serial presence-detect data: SDA is a bidirectional pin used to transfer
addresses and data into and data out of the presence-detect portion of
the module.
512MB (x72, ECC, SR): 168-PIN SDRAM RDIMM
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
©2001 Micron Technology, Inc. All rights reserved.