mt18lsdf6472y-133 Micron Semiconductor Products, mt18lsdf6472y-133 Datasheet - Page 17

• Manufacturer Part Number: mt18lsdf6472y-133
• Description: 512mb X72, Ecc, Sr 168-pin Sdram Rdimm
• Manufacturer: Micron Semiconductor Products

PDF: 09005aef80a2e32f/Source: 09005aef80d04a5a
SDF18C64x72G.fm - Rev. E 9/05 EN
23. The clock frequency must remain constant (stable clock is defined as a signal cycling
24. Auto precharge mode only. The precharge timing budget (
25. Precharge mode only.
26. JEDEC specifies three clocks.
27.
28. Parameter guaranteed by design.
29. For -13E, CL = 2 and
30. CKE is HIGH during refresh command period
31. Refer to device data sheet for timing waveforms.
32. The value of
33. This AC timing function will show an extra clock cycle when input register is in regis-
34. Leakage number reflects the worst case leakage possible through the module pin, not
within timing constraints specified for the clock pin) during access or precharge
states (READ, WRITE, including
used to reduce the data rate.
and 7.5ns for -133 after the first clock delay, after the last WRITE is executed. May not
exceed limit set for precharge mode.
t
limit is actually a nominal value and does not result in a fail value.
t
tered mode.
what each memory device contributes.
AC for -133/-13E at CL = 3 with no load is 4.6ns and is guaranteed by design.
RC -
t
RP = 45ns.
t
RAS used in -13E speed grade modules is calculated from
t
CK = 7.5ns; and for -133, CL = 3 and
512MB (x72, ECC, SR): 168-PIN SDRAM RDIMM
17
t
WR, and PRECHARGE commands). CKE may be
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RFC (MIN) else CKE is LOW. The I
t
CK = 7.5ns
t
RP) begins at 7ns for -13E;
©2001 Micron Technology, Inc. All rights reserved.
Notes
DD
6