hys64t128021hdl-3-b Infineon Technologies Corporation, hys64t128021hdl-3-b Datasheet - Page 24

• Manufacturer Part Number: hys64t128021hdl-3-b
• Description: 200-pin So-dimm Ddr2 Sdram Modules
• Manufacturer: Infineon Technologies Corporation

Table 16
Parameter
DQ output access time from CK /
CK
CAS A to CAS B command
period
CK, CK high-level width
CKE minimum high and low
pulse width
CK, CK low-level width
Auto-Precharge write recovery +
precharge time
Minimum time clocks remain ON
after CKE asynchronously drops
LOW
DQ and DM input hold time
(differential data strobe)
DQ and DM input hold time
(single ended data strobe)
DQ and DM input pulse width
(each input)
DQS output access time from CK
/ CK
DQS input low (high) pulse width
(write cycle)
DQS-DQ skew (for DQS &
associated DQ signals)
Write command to 1st DQS
latching transition
DQ and DM input setup time
(differential data strobe)
DQ and DM input setup time
(single ended data strobe)
DQS falling edge hold time from
CK (write cycle)
DQS falling edge to CK setup
time (write cycle)
Clock half period
Data-out high-impedance time
from CK / CK
Address and control input hold
time
Address and control input pulse
width
(each input)
Data Sheet
Timing Parameter by Speed Grade - DDR2-400 & DDR2-533
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AC
CCD
CH
CKE
CL
DAL
DELAY
DH
DH1
DIPW
DQSCK
DQSL,H
DQSQ
DQSS
DS
DS1
DSH
DSS
HP
HZ
IH
IPW
(base)
(base) 225
(base)
(base) –25
(base) –25
Min.
DDR2–533
–500
2
0.45
3
0.45
WR +
t
0.35
–450
0.35
—
WL – 0.25
100
0.2
0.2
MIN. (
—
375
0.6
IS
+
t
CK
t
t
CL,
RP
+
24
t
t
IH
CH
)
Max.
+500
—
0.55
—
0.55
—
––
––
—
—
—
300
WL + 0.25 WL – 0.25
—
—
—
—
t
—
—
AC.MAX
450
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
SO-DIMM DDR2 SDRAM Module
DDR2–400
275
150
475
Min.
–600
2
0.45
3
0.45
WR +
t
–25
0.35
–500
0.35
—
–25
0.2
0.2
MIN. (
—
0.6
IS
+
t
CK
t
t
CL,
RP
+
t
t
IH
CH
)
Max.
+600
—
0.55
—
0.55
—
––
––
—
—
—
350
WL + 0.25
—
—
—
—
t
—
—
Electrical Characteristics
AC.MAX
500
05122005-2TKP-OM7N
Rev 1.00, 2005-06
Unit Notes
ps
t
t
t
t
t
ns
ps
ps
t
ps
t
ps
t
ps
ps
t
t
ps
ps
t
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
1)