m471b5273bh1 Samsung Semiconductor, Inc., m471b5273bh1 Datasheet
m471b5273bh1
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Unbuffered SoDIMM DDR3 SDRAM Specification 204pin Unbuffered SODIMM based on 2Gb B-die 78FBGA with Lead-Free & Halogen-Free INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL ...
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... Address Configuration ............................................................................................................................................... 4 4.0 x64 DIMM Pin Configurations (Front side/Back side).............................................................................................. 5 5.0 Pin Description............................................................................................................................................................ 6 6.0 Input/Output Functional Description ........................................................................................................................ 7 7.0 Functional Block Diagram: ........................................................................................................................................ 8 7.1 4GB, 512Mx64 Module(Populated as 2 rank of x8 DDR3 SDRAMs) ................................................................. 8 8.0 Absolute Maximum Ratings ....................................................................................................................................... 9 8.1 Absolute Maximum DC Ratings........................................................................................................................... 9 8.2 DRAM Component Operating Temperature Range............................................................................................ 9 9.0 AC & DC Operating Conditions ................................................................................................................................. 9 9.1 Recommended DC Operating Conditions (SSTL - 15)....................................................................................... 9 10.0 AC & ...
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Unbuffered SoDIMM Revision History Revision Month Year 1.0 December 2008 - First Release History DDR3 SDRAM Rev. 1.0 December 2008 ...
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... Unbuffered SoDIMM 1.0 DDR3 Unbuffered SoDIMM Ordering Information Part Number M471B5273BH1-CF8/ 1066Mbps 7-7- 1333Mbps 9-9-9 2.0 Key Features DDR3-1066 Speed tCK(min) CAS Latency tRCD(min) tRP(min) tRAS(min) tRC(min) • JEDEC standard 1.5V ± 0.075V Power Supply • 1.5V ± 0.075V DDQ • 533MHz f for 1066Mb/sec/pin, 667MHz f CK • ...
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... Note : Connect Not Useable, RFU = Reserved Future Use 2. TEST(pin 125) is reserved for bus analysis probes and normal memory modules. 3. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor. SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. ...
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Unbuffered SoDIMM 5.0 Pin Description Pin Name Description CK0, CK1 Clock Inputs, positive line CK0, CK1 Clock Inputs, negative line CKE0, CKE1 Clock Enables RAS Row Address Strobe CAS Column Address Strobe WE Write Enable S0, S1 Chip Selects A0-A9, ...
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... Input Address pins used to select the Serial Presence Detect and Temp sensor base address. TEST I/O The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules RESET Input RESET In Active Low This signal resets the DDR3 SDRAM Function on the system planar to act as a pull up ...
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... Unbuffered SoDIMM 7.0 Functional Block Diagram: 7.1 4GB, 512Mx64 Module (Populated as 2 rank of x8 DDR3 SDRAMs) Ω 240 DQS3 DQS ± 1% DQS3 DQS ZQ DM3 DM DQ[24:31] DQ[0:7] D11 Ω 240 DQS1 DQS ± 1% DQS1 DQS ZQ DM1 DM DQ[0:7] DQ[8:15] D1 Ω 240 DQS0 DQS ± 1% DQS0 DQS ZQ DM0 DM DQ[0:7] DQ[0:7] D0 Ω ...
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Unbuffered SoDIMM 8.0 Absolute Maximum Ratings 8.1 Absolute Maximum DC Ratings Symbol Parameter V Voltage on V pin relative Voltage on V pin relative to V DDQ DDQ V V Voltage on any pin relative ...
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Unbuffered SoDIMM 10.0 AC & DC Input Measurement Levels 10.1 AC and DC Logic Input Levels for Single-ended Signals Single Ended AC and DC input levels for Command and Address Symbol Parameter V (DC) DC input logic high IH.CA V ...
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Unbuffered SoDIMM 10.2 V Tolerances. REF The dc-tolerance limits and ac-noise limits for the reference voltages function of time. (V stands for V REF REF V (DC) is the linear average of V (t) over ...
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Unbuffered SoDIMM 10.3 AC and DC Logic Input Levels for Differential Signals 10.3.1 Differential Signals Definition V .DIFF.AC.MIN .DIFF.AC.MAX IL Figure 3 : Definition of differential ac-swing and "time above ac level" tDVAC 10.3.2 ...
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Unbuffered SoDIMM 10.3.3 Single-ended Requirements for Differential Signals Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately ...
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Unbuffered SoDIMM 10.3.4 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) ...
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Unbuffered SoDIMM 11.0 AC and DC Output Measurement Levels 11.1 Single Ended AC and DC Output Levels Single Ended AC and DC output levels Symbol Parameter V (DC) DC output high measurement level (for IV curve linearity (DC) ...
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Unbuffered SoDIMM 11.4 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V V (AC) for differential signals as shown in below. OHdiff Differential Output ...
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Unbuffered SoDIMM 12.0 IDD specification definition Symbol Description Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 30 ; BL: 8 IDD0 Inputs: partially toggling according to Table 32 ; Data IO: MID-LEVEL; ...
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Unbuffered SoDIMM Symbol Description Self-Refresh Current: Extended Temperature Range (optional) TCASE 95°C; Auto Self-Refresh (ASR): Disabled IDD6ET a) LOW; CL: see Table AL: 0; CS, Command, Address, Bank Address, Data IO: MID-LEVEL;DM:stable at ...
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... Unbuffered SoDIMM 12.1 IDD SPEC Table M471B5273BH1 : 4GB (512Mx64) Module Symbol (DDR3-1066@CL=7) IDD0 IDD1 IDD2P0(slow exit) IDD2P1(fast exit) IDD2N IDD2Q IDD3P(fast exit) IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 13.0 Input/Output Capacitance Parameter Input/output capacitance (DQ, DM, DQS, DQS, TDQS, TDQS) Input capacitance (CK and CK) ...
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Unbuffered SoDIMM 14.0 Electrical Characteristics and AC timing (0 °C<T ≤95 ° 1.5V ± 0.075V; V CASE DDQ 14.1 Refresh Parameters by Device Density Parameter All Bank Refresh to active/refresh cmd time Average periodic refresh interval Note : ...
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Unbuffered SoDIMM 14.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin. DDR3-1066 Speed Bins Speed CL-nRCD-nRP Parameter Intermal read command to ...
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Unbuffered SoDIMM 14.3.1 Speed Bin Table Notes Absolute Specification ( OPER DDQ DD Note : 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need ...
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Unbuffered SoDIMM 15.0 Timing Parameters for DDR3-800, DDR3-1066 and DDR3-1333 Timing Parameters by Speed Bin Speed Parameter Clock Timing Minimum Clock Cycle Time (DLL off mode) Average Clock Period Clock Period Average high pulse width Average low pulse width Clock ...
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Unbuffered SoDIMM Timing Parameters by Speed Bin (Cont.) Speed Parameter Command and Address Timing DLL locking time internal READ Command to PRECHARGE Command delay Delay from start of internal write transaction to internal read command WRITE recovery time Mode Register ...
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Unbuffered SoDIMM Timing Parameters by Speed Bin (Cont.) Speed Parameter Power Down Timing Exit Power Down with DLL on to any valid command;Exit Percharge Power Down with DLL frozen to commands not requiring a locked DLL Exit Precharge Power Down ...
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Unbuffered SoDIMM 15.1 Jitter Notes Specific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; ...
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Unbuffered SoDIMM 15.2 Timing Parameter Notes 1. Actual value dependant upon measurement level definitions which are TBD. 2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands. 3. The max values are system dependent ...
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... Unbuffered SoDIMM 16.0 Physical Dimensions : 16.1 256Mbx8 based 512Mx64 Module(2 Ranks) 2X 1.80 0. (OPTIONAL HOLES) 1.00 ± 0.10 Detail A The used device is 256M x8 DDR3 SDRAM, FBGA. DDR3 SDRAM Part NO : K4B2G0846B - HC** 67.60 3.00 0.60 0.45 ± 0.03 4.00 ± 0.10 2.55 0.25 MAX Detail DDR3 SDRAM Units : Millimeters Max 3.8 1.00 ± 0.10 2X 4.00 ± 0.10 0. Rev. 1.0 December 2008 ...