m471b5273bh1 Samsung Semiconductor, Inc., m471b5273bh1 Datasheet - Page 2

• Manufacturer Part Number: m471b5273bh1
• Description: Ddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

Table Contents
1.0 DDR3 Unbuffered SoDIMM Ordering Information .................................................................................................... 4
2.0 Key Features ............................................................................................................................................................... 4
3.0 Address Configuration ............................................................................................................................................... 4
4.0 x64 DIMM Pin Configurations (Front side/Back side).............................................................................................. 5
5.0 Pin Description............................................................................................................................................................ 6
6.0 Input/Output Functional Description ........................................................................................................................ 7
7.0 Functional Block Diagram: ........................................................................................................................................ 8
8.0 Absolute Maximum Ratings ....................................................................................................................................... 9
9.0 AC & DC Operating Conditions ................................................................................................................................. 9
10.0 AC & DC Input Measurement Levels ..................................................................................................................... 10
11.0 AC and DC Output Measurement Levels .............................................................................................................. 15
12.0 IDD specification definition.................................................................................................................................... 17
13.0 Input/Output Capacitance ...................................................................................................................................... 19
14.0 Electrical Characteristics and AC timing.............................................................................................................. 20
15.0 Timing Parameters for DDR3-800, DDR3-1066 and DDR3-1333.......................................................................... 23
16.0 Physical Dimensions : ........................................................................................................................................... 28
Unbuffered SoDIMM
7.1 4GB, 512Mx64 Module(Populated as 2 rank of x8 DDR3 SDRAMs) ................................................................. 8
8.1 Absolute Maximum DC Ratings........................................................................................................................... 9
8.2 DRAM Component Operating Temperature Range............................................................................................ 9
9.1 Recommended DC Operating Conditions (SSTL - 15)....................................................................................... 9
10.1 AC and DC Logic Input Levels for Single-ended Signals.............................................................................. 10
10.2 VREF Tolerances. ............................................................................................................................................. 11
10.3 AC and DC Logic Input Levels for Differential Signals ................................................................................. 12
10.4 Slew Rate Definition for Single Ended Input Signals .................................................................................... 14
10.5 Slew rate definition for Differential Input Signals .......................................................................................... 14
11.1 Single Ended AC and DC Output Levels ........................................................................................................ 15
11.2 Differential AC and DC Output Levels ............................................................................................................ 15
11.3 Single Ended Output Slew Rate ...................................................................................................................... 15
11.4 Differential Output Slew Rate .......................................................................................................................... 16
12.1 IDD SPEC Table................................................................................................................................................. 19
14.1 Refresh Parameters by Device Density .......................................................................................................... 20
14.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ....................................................... 20
14.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin........................................................ 21
15.1 Jitter Notes ........................................................................................................................................................ 26
15.2 Timing Parameter Notes................................................................................................................................... 27
16.1 256Mbx8 based 512Mx64 Module(2 Ranks)................................................................................................... 28
10.3.1 Differential Signals Definition ................................................................................................................. 12
10.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) .................................. 12
10.3.3 Single-ended Requirements for Differential Signals ............................................................................ 13
10.3.4 Differential Input Cross Point Voltage ................................................................................................... 14
14.3.1 Speed Bin Table Notes ............................................................................................................................ 22
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Rev. 1.0 December 2008
DDR3 SDRAM