m471b5273bh1 Samsung Semiconductor, Inc., m471b5273bh1 Datasheet - Page 18

• Manufacturer Part Number: m471b5273bh1
• Description: Ddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
c) Pecharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
e) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
f) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device
g) IDD current measure method and detail patterns are described on DDR3 component datasheet
Unbuffered SoDIMM
IDD6ET
IDD6TC
IDD7
Symbol
Description
Self-Refresh Current: Extended Temperature Range (optional)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled
LOW; CL: see Table 30 ; BL: 8
Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers
Auto Self-Refresh Current (optional)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Enabled
LOW; CL: see Table 30 ; BL: 8
Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 30 ; BL: 8
Address, Bank Address Inputs: partially toggling according to Table 39 ; Data IO: read data bursts with different data between one burst and the next one
according to Table 39 ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 39 ; Output
Buffer and RTT: Enabled in Mode Registers
a)
a)
; AL: 0; CS, Command, Address, Bank Address, Data IO: MID-LEVEL;DM:stable at 0; Bank Activity: Extended Temperature
; AL: 0; CS, Command, Address, Bank Address, Data IO: MID-LEVEL; DM:stable at 0; Bank Activity: Auto
f
)
b)
; ODT Signal: stable at 0; Pattern Details: see Table 39
d)
d)
; Self-Refresh Temperature Range (SRT): Normal
; Self-Refresh Temperature Range (SRT): Extended
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f
)
b)
b)
; ODT Signal: MID-LEVEL
; ODT Signal: MID-LEVEL
a, g)
; AL: CL-1; CS: High between ACT and RDA; Command,
Rev. 1.0 December 2008
e)
; CKE: Low; External clock: Off; CK and CK:
e)
; CKE: Low; External clock: Off; CK and CK:
DDR3 SDRAM