m471b5273bh1 Samsung Semiconductor, Inc., m471b5273bh1 Datasheet - Page 23

• Manufacturer Part Number: m471b5273bh1
• Description: Ddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

Timing Parameters by Speed Bin
15.0 Timing Parameters for DDR3-800, DDR3-1066 and DDR3-1333
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
Average Clock Period
Clock Period
Average high pulse width
Average low pulse width
Clock Period Jitter
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
Cycle to Cycle Period Jitter during DLL locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
Cumulative error across n = 13, 14 ... 49, 50 cycles
Absolute clock HIGH pulse width
Absolute clock Low pulse width
Data Timing
DQS,DQS to DQ skew, per group, per access
DQ output hold time from DQS, DQS
DQ low-impedance time from CK, CK
DQ high-impedance time from CK, CK
Data setup time to DQS, DQS referenced to V
Data hold time to DQS, DQS referenced to V
DQ and DM Input pulse width for each input
Data Strobe Timing
DQS, DQS READ Preamble
DQS, DQS differential READ Postamble
DQS, DQS output high time
DQS, DQS output low time
DQS, DQS WRITE Preamble
DQS, DQS WRITE Postamble
DQS, DQS rising edge output access time from rising CK, CK
DQS, DQS low-impedance time (Referenced from RL-1)
DQS, DQS high-impedance time (Referenced from RL+BL/2)
DQS, DQS differential input low pulse width
DQS, DQS differential input high pulse width
DQS, DQS rising edge to CK, CK rising edge
DQS,DQS faling edge setup time to CK, CK rising edge
DQS,DQS faling edge hold time to CK, CK rising edge
Unbuffered SoDIMM
Parameter
Speed
IH
IH
(AC)V
(AC)V
IL
IL
(AC) levels
(AC) levels
tCK(DLL_OF
tERR(10per)
tERR(11per)
tERR(12per)
tJIT(per, lck)
tJIT(cc, lck)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(nper)
tDS(base)
tDH(base)
tHZ(DQS)
tLZ(DQS)
tCK(avg)
tCK(abs)
tCH(avg)
tCL(avg)
tCH(abs)
tCL(abs)
tDQSCK
Symbol
tJIT(per)
tLZ(DQ)
tHZ(DQ)
tJIT(cc)
tDQSQ
tWPRE
tRPRE
tWPST
tDQSH
tDQSS
tDIPW
tRPST
tDQSL
23 of 28
tQSH
tQSL
tDSS
tDSH
tQH
F)
tCK(avg)min +
tJIT(per)min
- 132
- 157
- 175
- 188
- 200
- 209
- 217
- 224
- 231
- 237
- 242
-0.25
0.47
0.47
0.43
0.43
0.38
-600
0.38
0.38
-300
-600
0.45
0.45
MIN
100
490
-90
-80
0.9
0.3
0.9
0.3
0.2
0.2
25
8
-
-
-
DDR3-1066
180
160
tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
tCK(avg)max +
tJIT(per)max
Note 19
Note 11
MAX
0.53
0.53
0.55
0.55
0.25
132
157
175
188
200
209
217
224
231
237
242
150
300
300
300
300
300
90
80
-
See Speed Bins Table
-
-
-
-
-
-
-
-
-
-
-
-
tCK(avg)min +
Rev. 1.0 December 2008
tJIT(per)min
- 118
- 140
- 155
- 168
- 177
- 186
- 193
- 200
- 205
- 210
- 215
-0.25
-500
-255
-500
MIN
0.47
0.47
0.43
0.43
0.38
0.45
0.45
400
-80
-70
0.9
0.3
0.4
0.4
0.9
0.3
0.2
0.2
30
65
8
-
-
-
DDR3-1333
160
140
DDR3 SDRAM
tCK(avg)max +
tJIT(per)max
Note 19
Note 11
MAX
0.53
0.53
0.55
0.55
0.25
118
140
155
168
177
186
193
200
205
210
215
125
250
250
255
250
250
80
70
-
-
-
-
-
-
-
-
-
-
-
-
-
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
Units
tCK
tCK
tCK
tCK
tCK
tCK
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
13, 19, g
11, 13, b
12,13,14
13,14, f
13,14, f
13,14,f
29, 31
30, 31
Note
13, g
d, 17
d, 17
13, g
13, g
c, 32
c, 32
13,f
24
25
26
13
28
6
c