mt9v112 Micron Semiconductor Products, mt9v112 Datasheet - Page 37

• Manufacturer Part Number: mt9v112
• Description: 1/6-inch Soc Vga Cmos Digital Image Sensor
• Manufacturer: Micron Semiconductor Products

T able 12: Sensor Core Register Descriptions
09005aef8154a39d/09005aef8175e6cc
MT9V112_2.fm- Rev. A 1/05 EN
R0:0—0x000 – Chip Version (R/O)
Bits 15:0
R1:0—0x001 – Row Start
Bits 10:0
Row Start
R2:0—0x002 – Column Start
Bits 10:0
Col Start
R3:0—0x003 – Row Width
Bits 10:0
Row Width
R4:0—0x004 – Column Width
Bits 10:0
Col Width
R5:0—0x005 – Horizontal Blanking—Context B
Bits 10:0
Horizontal
Blanking B
R6:0—0x006 – Vertical Blanking—Context B
Bits 14:0
Vertical
Blanking B
R7:0—0x007 – Horizontal Blanking—Context A
Bits 10:0
Horizontal
Blanking A
R8:0—0x008 – Vertical Blanking—Context A
Bits 14:0
Vertical
Blanking A
R9:0—0x009 – Shutter Width
Bits 15:0
Shutter
Width
R10:0—0x00A – Row Speed
Bit 13
Bit 8
Invert Pixel
Clock
BIT FIELD
Hardwired READ only.
The first row to be read out (not counting dark rows that may
be read). To window the image down, set this register to the
starting Y value. Setting a value less than 8 is not recommended
since the dark rows should be read using Reg0x022.
The first column to be read out (not counting dark columns that
may be read). To window the image down, set this register to
the starting X value. Setting a value below 0x18 is not
recommended since readout of dark columns should be
controlled by Reg0x022.
Number of rows in the image to be read out (not counting dark
rows or border rows that may be read).
Number of columns in image to be read out (not counting dark
columns or border columns that may be read).
Number of blank columns in a row when context B is chosen (bit
0, Reg0x0C8 = 1). The extra columns are added at the beginning
of a row. The minimum supported value is 132.
Number of blank rows in a frame when context B is chosen (bit
1, Reg0x0C8 = 1). This number must be equal to or larger than
the number of dark rows read out in a frame specified by
Reg0x022.
Number of blank columns in a row when context A is chosen (bit
0, Reg0x0C8 = 0). The extra columns are added at the beginning
of a row. The minimum supported value is 132.
Number of blank rows in a frame when context A is chosen (bit
1, Reg0x0C8 = 1). This number must be equal to or larger than
the number of dark rows read out in a frame specified by
Reg0x022.
Integration time in number of rows. In addition to this register,
the shutter delay register (Reg0x0C) and the overhead time
influences the integration time for a given row time.
Invert to cb clock.
Invert pixel clock. When set, LINE_VALID, FRAME_VALID, and
DATA_OUT is set to the falling edge of PIXCLK. When clear, they
are set to the rising edge if there is no pixel clock delay.
DESCRIPTION
37
SOC VGA DIGITAL IMAGE SENSOR
Micron Technology, Inc., reserves the right to change products or specificat ions wit hout not ice.
DEFAULT
0x1229
(HEX)
0x1D6
0x1E0
0x284
0x12
0x26
0xCB
0x0B
0xCB
0xB
0x0
—
SYNC’D TO
FRAME
START
©2004 Micron Technology, Inc. All rights reserved.
—
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
PRELIMINARY
MT9V112
FRAME
BAD
YM
YM
YM
YM
YM
YM
—
N
N
N
0
WRITE
READ/
W
W
W
W
W
W
W
W
W
—
W
R