mt9v112 Micron Semiconductor Products, mt9v112 Datasheet - Page 47

• Manufacturer Part Number: mt9v112
• Description: 1/6-inch Soc Vga Cmos Digital Image Sensor
• Manufacturer: Micron Semiconductor Products

Reset, Clocks, and Standby
Reset
It is active LOW . In this reset state, all control registers
have the default values.
serial interface program. In soft-reset mode, the two-
wire serial interface and register ring bus are still run-
ning. All control registers are reset using default values.
See R13:0.
Clocks
clock coming from the CLKIN signal, and a pixel clock
via a clock-gated operation running at half frequency
of the master clock. All device clocks are turned off in
power-down mode. When the MT9V112 operates in
sensor stand-alone mode, the image flow pipeline
clocks can be shut off to conserve power. See R13:0 on
page 38.
in a dual-camera application, the MT9V112 employs a
divide-by-two clock option, allowing a 54 MHz input to
the master clock. For more information about this fea-
ture, see the R13:0 register description on page 38 in
Table 12.
Standby
power-down, device addressing, and tri-state func-
tions. Table 17 shows how STANDBY affects the out-
put signal state.
09005aef8154a39d/09005aef8175e6cc
MT9V112_2.fm- Rev. A 1/05 EN
Power-up reset is asserted/de-asserted on RESET#.
Soft reset is asserted/ de-asserted by the two-wire
The MT9V112 has two primary clocks; a master
When the MT9V112 is operated with the MT9M111
STA NDBY is a multifunctional signal that controls
47
SOC VGA DIGITAL IMAGE SENSOR
It is active HIGH. In this hard standby state, all internal
clocks are turned off and the analog block is in standby
mode to save power consumption. The signal state is
High-Z when R13[4] = 0 and R13[6] = 0.
result of S
is “0”.) The R13:0[10] bit is not writable when
STA NDBY is asserted “1.”
serial interface to R13:0[2]. In soft standby, all internal
clocks are turned off, the analog block is in standby
mode, but the signal state is not affected. Following the
assertion of either hard or soft standby, the analog cir-
cuitry completes reading the current row and then
enters the standby state. It is necessary to keep clock-
ing the sensor for an entire row time to ensure proper
entry into the standby state.
T able 17: ST ANDBY Effect on the
R13:0[6]
SIGNAL
DRIVE
Hard standby is asserted/de-asserted on STANDBY .
Two-wire interface ID addressing is based on the
Soft standby is asserted/de-asserted by a two-wire
.
0
0
1
x
Micron Technology, Inc., reserves the right to change products or specificat ions wit hout not ice.
ADDR
DISABLE
R13:0[4]
OUTPUT
Output State
XOR R13:0[10]. (The R13:0[10] default
0
0
0
1
ST ANDBY
©2004 Micron Technology, Inc. All rights reserved.
0
1
x
x
PRELIMINARY
MT9V112
OUTPUT STATE
High-Z
High-Z
Driven
Driven