npe405h Applied Micro Circuits Corporation (AMCC), npe405h Datasheet - Page 12
npe405h
Manufacturer Part Number
npe405h
Description
Powernp Npe405h Embedded Processor
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet
1.NPE405H.pdf
(70 pages)
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NPe405H – PowerNP NPe405H Embedded Processor
HDLCEX INTERFACE
HDLCMP INTERFACE
GENERAL PURPOSE IO (GPIO) CONTROLLER
UNIVERSAL INTERRUPT CONTROLLER (UIC)
Two cascaded Universal Interrupt Controllers (UICs) provide the control, status, and communications necessary
for the interrupt sources and the PowerPC processor.
Features include:
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DS2011
32-channel HDLC controller
Two full-duplex Pulse Code Modulation (PCM) Highway ports at speeds up to 4.096 Mbps per port or 8.192
Mbps when using a single port
Supports HDLC protocol as well as a Transparent mode
For a single channel per port, autonomous management of I-Frames and S-Frames of the Normal
Response mode (NRM) protocol on one channel per port. U-frames are handled by software.
Supports software emulation of NRM on all channels
HDLC controller provides eight full-duplex serial ports
Up to 2.048Mbps data rate
Supports HDLC protocol as well as a Transparent mode
Software emulation of NRM
Two GPIO controllers
- 32-signal system GPIO (GPIO0)
- 32-signal communications GPIO (GPIO1)
Most GPIOs are pin-shared with other functions. Configuration registers are provided to determine whether
a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose. Both GPIO func-
tions have 32 I/Os.
Each GPIO output is separately programmable to emulate an open-drain driver (drives to zero, three-stated
if output bit is 1)
Seven external and 49 internal interrupts
Edge triggered or level-sensitive
Positive or negative active
Selectable non-critical or critical interrupt requests to the PPC405 processor core
Programmable critical interrupt priority ordering
Programmable critical interrupt vector generation for reduced latency interrupt handling
Revision 1.02 – November 16, 2007
Data Sheet
AMCC Proprietary
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