npe405h Applied Micro Circuits Corporation (AMCC), npe405h Datasheet - Page 43

• Manufacturer Part Number: npe405h
• Description: Powernp Npe405h Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

NPe405H – PowerNP NPe405H Embedded Processor
SIGNAL FUNCTIONAL DESCRIPTION
Table 6. Signal Functional Description (Sheet 1 of 9)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.
AMCC Proprietary
PCI Interface
PCIC3:0[BE3:0]
PCIReq0[Gnt]
PCIGnt0[Req]
Signal Name
PCIAD0:31
PCIDevSel
PCIReq1:5
PCIFrame
PCITRDY
PCIReset
PCIParity
PCIIDSel
PCIIRDY
PCIStop
PCISErr
PCIPErr
PCIINT
PCIClk
PCI Address/Data bus. Multiplexed address and data bus
PCI bus command or Byte Enable
PCI Parity. Parity is even across PCIAD0:31 and
PCIC0:3[BE0:3]. PCIParity is valid one cycle after either an
address or data phase. The PCI device that drove PCIAD0:31
is responsible for driving PCIParity on the next PCI bus clock.
Driven by the current PCI bus master to indicate the
beginning and duration of a PCI access.
Driven by the current PCI bus master. Assertion of PCIIRDY
indicates that the PCI initiator is ready to transfer data.
The target of the current PCI transaction drives PCITRDY.
Assertion of PCITRDY indicates that the PCI target is ready to
transfer data.
The target of the current PCI transaction can assert PCIStop
to indicate to the requesting PCI master that it wants to end
the current transaction.
Driven by the target of the current PCI transaction. A PCI
target asserts PCIDevSel when it has decoded an address
and command encoding and claims the transaction.
Used during configuration cycles to select the PCI slave
interface for configuration
Used for reporting address parity errors or catastrophic
failures detected by a PCI target.
Used for reporting data parity errors on PCI transactions.
PCIPErr is driven active by the device receiving PCIAD0:31,
PCIC0:3[BE0:3], and PCIParity, two PCI clocks following the
data in which bad parity is detected.
Used as the asynchronous PCI clock.
PCI specific reset
PCI Interrupt. Open-drain output (two states; 0 or open
circuit).
Req0 when internal arbiter is used, or Gnt when external
arbiter is used. IF PCI bus is used, pull this signal up;
otherwise, pull down.
Used as PCIReq1:5 input when internal arbiter is used
Gnt0 when internal arbiter is used, or Req when external
arbiter is used
Description
Revision 1.02 – November 16, 2007
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
I
I
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
Type
Data Sheet
DS2011
Notes
4
4
4
4
4
5
4
4
4
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