npe405h Applied Micro Circuits Corporation (AMCC), npe405h Datasheet - Page 63

• Manufacturer Part Number: npe405h
• Description: Powernp Npe405h Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

NPe405H – PowerNP NPe405H Embedded Processor
Table 15. I/O Specifications—133 and 200MHz (Sheet 2 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
3. SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load.
4. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS
5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
AMCC Proprietary
HDLCEXTxClk
HDLCEXTxDataA:B
HDLCEXTxFS
[HDLCEXTxEnA:B]
HDLCMP Interface
HDLCMPTxClk0:3
[HDLCMPTxClk4:7]
HDLCMPTxData0:3
[HDLCMPTxData4]
[HDLCMPTxData5]
[HDLCMPTxData6]
[HDLCMPTxData7]
[HDLCMPTxEn0]
[HDLCMPTxEn1]
[HDLCMPTxEn2]
[HDLCMPTxEn3]
[HDLCMPTxEn4]
[HDLCMPTxEn5]
[HDLCMPTxEn6]
[HDLCMPTxEn7]
HDLCMPRxClk0:3
[HDLCMPRxClk4:7]
HDLCMPRxData0:3
[HDLCMPRxData4]
[HDLCMPRxData5]
[HDLCMPRxData6]
[HDLCMPRxData7]
Trace Interface
[TrcClk]
[TS1E]
[TS2E]
[TS1O]
[TS2O]
[TS3:4]
command is used by SDRAM. Output times in table are in cycle 1.
model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that
the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
Signal
Setup Time
(T
[24.9]
[24.7]
[24.6]
[24.8]
IS
24.4
22.8
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
min)
Input (ns)
Hold Time
(T
IH
[0.1]
[0.1]
[0.1]
[0.1]
n/a
n/a
0.7
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
0.5
n/a
n/a
n/a
n/a
n/a
n/a
min)
Valid Delay
(T
OV
[10.0]
[12.2]
10.5
[9.9]
[9.8]
[9.8]
[9.8]
[9.9]
[9.4]
[9.5]
[9.9]
[9.8]
[9.8]
[9.9]
[7.2]
[7.2]
[7.2]
[7.2]
[7.2]
n/a
n/a
n/a
9.9
n/a
n/a
9.3
n/a
n/a
n/a
n/a
n/a
n/a
max)
Output (ns)
Hold Time
(T
OH
[3.3]
[2.8]
[3.0]
[3.0]
[2.9]
[2.9]
[2.9]
[2.9]
[3.3]
[2.8]
[3.0]
[3.0]
[2.5]
[2.0]
[2.0]
[2.0]
[2.0]
[2.0]
n/a
3.3
n/a
3.0
n/a
n/a
3.0
n/a
n/a
n/a
n/a
n/a
n/a
n/a
min)
(maximum)
Output Current (mA)
I/O H
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
Revision 1.02 – November 16, 2007
(minimum)
I/O L
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Data Sheet
Clock
DS2011
Notes
63