k4r881869e Samsung Semiconductor, Inc., k4r881869e Datasheet - Page 14

• Manufacturer Part Number: k4r881869e
• Description: 288mbit Rdram 512k X 18bit X 32s Banks
• Manufacturer: Samsung Semiconductor, Inc.

K4R881869E
Timing Conditions
t
t
t
t
t
t
t
t
t
t
t
t
t
CYCLE
CR
CH
TR
DCW
DR
S
DR1,
DR2,
CYCLE1
CH1
S1
H1
, t
, t
, t
, t
H
, t
Symbol
CF
CL
DF
t
t
DF1
DF2
CL1
CTM and CFM cycle times (-1200)
CTM and CFM cycle times (-1066)
CTM and CFM cycle times (-800)
CTM and CFM input rise and fall times. Use the minimum value of
these parameters during testing. (-1200)
CTM and CFM input rise and fall times. Use the minimum value of
these parameters during testing. (-1066,-800)
CTM and CFM high and low times
CTM-CFM differential (MSE/MS=0/0)
CTM-CFM differential (MSE/MS=1/1)
CTM-CFM differential for 1.875ns and 1.667ns (MSE/MS=1/0)
Domain crossing window
DQA/DQB/ROW/COL input rise/fall times (20% to 80%). Use the
minimum value of these parameters during testing.@ t
CYCLE
DQA/DQB/ROW/COL input rise/fall times (20% to 80%). Use the
minimum value of these parameters during testing.@ t
CYCLE
DQA/DQB/ROW/COL input rise/fall times (20% to 80%). Use the
minimum value of these parameters during testing.@ t
CYCLE
DQA/DQB/ROW/COL-to-CFM set/hold @ t
DQA/DQB/ROW/COL-to-CFM set/hold @ t
DQA/DQB/ROW/COL-to-CFM set/hold @ t
SIO0, SIO1 input rise and fall times
CMD, SCK input rise and fall times
SCK cycle time - Serial control register transactions
SCK cycle time - Power transitions @ t
SCK cycle time - Power transitions @ t
SCK cycle time - Power transitions @ t
SCK high and low times @ t
SCK high and low times @ t
SCK high and low times @ t
CMD setup time to SCK rising or falling edge
CMD setup time to SCK rising or falling edge
CMD setup time to SCK rising or falling edge
CMD hold time to SCK rising or falling edge
=1.667ns
=1.875ns
=2.50ns
Parameter
CYCLE
CYCLE
CYCLE
Table 11: Timing Conditions
=1.667ns
=1.875ns
=2.50ns
a
CYCLE
CYCLE
CYCLE
e
CYCLE
CYCLE
CYCLE
e
e
e
=1.667ns
=1.875ns
=2.50ns
@ t
@ t
@ t
Page 12
CYCLE
CYCLE
CYCLE
=1.667ns
=1.875ns
=2.50ns
=1.667ns
=1.875ns
=2.50ns
0.200
0.160
0.140
1.667
1.875
Min
1000
40%
4.25
1.25
2.50
-0.1
-0.1
0.2
0.2
0.0
0.9
0.2
0.2
0.2
7.5
7.5
3.5
3.5
1.0
1.0
10
1
-
-
b.d
b,c
b
Version 1.4 Dec. 2003
Max
60%
3.33
0.45
0.45
0.45
0.65
2.5
2.5
0.5
1.0
1.0
0.1
0.1
5.0
2.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Direct RDRAM
t
t
t
CYCLE
CYCLE
CYCLE
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure(s)
Figure 56
Figure 56
Figure 56
Figure 43
Figure 56
Figure 62
Figure 57
Figure 57
Figure 59
Figure 59
Figure 59
Figure 59
Figure 59
Figure 59
™