k4r881869e Samsung Semiconductor, Inc., k4r881869e Datasheet - Page 15

• Manufacturer Part Number: k4r881869e
• Description: 288mbit Rdram 512k X 18bit X 32s Banks
• Manufacturer: Samsung Semiconductor, Inc.

K4R881869E
CLE
a. MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is effectively 0.0 to 0.0.
b. t
c. This parameter also applies to a-1200 part when operated with t
d. This parameter also applies to a-1200 or -1066 part when operated with t
e. With V
f. Effective hold becomes t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
S2
H2
S3
H3
S4
H4
NPQ
READTOCC
CCSAMTOREAD
CE
CD
FRM
NLIMIT
REF
BURST
CCTRL
TEMP
TCEN
TCAL
TCQUIET
PAUSE
+t
S,MIN
PDNXB,MAX
Symbol
IL,CMOS
and t
H,MIN
]. See Figure 50
=0.5V
for other t
CMOS
SIO0 setup time to SCK falling edge
SIO0 hold time to SCK falling edge
PDEV setup time on DQA5..0 to SCK rising edge.
PDEV hold time on DQA5..0 to SCK rising edge.
ROW2..0, COL4..0 setup time for quiet window
ROW2..0, COL4..0 hold time for quiet window
Quiet on ROW/COL bits during NAP/PDN entry
Offset between read data and CC packets (same device)
Offset between CC packet and read data (same device)
CTM/CFM stable before NAP/PDN exit
CTM/CFM stable after NAP/PDN entry
ROW packet to COL packet ATTN framing delay
Maximum time in NAP mode
Refresh interval
Interval after PDN or NAP (with self-refresh) exit in which all
banks of the RDRAM device must be refreshed at least once.
Current control interval
Temperature control interval
TCE command to TCAL command
TCAL command to quiet window
Quiet window (no read data)
RDRAM device delay (no RSL operations allowed)
H4
’=t
-0.4V and V
CYCLE
H4
+[PDNXA•64•t
values can be interpolated between or extrapolated from the timings at the 2 specified t
IH,CMOS
SCYCLE
=0.5V
Parameter
CMOS
+t
Table 11: Timing Conditions
PDNXB,MAX
+0.4V
CYCLE
f
]-[PDNX•256•t
= 1.875ns
Page 13
CYCLE
= 2.50ns
SCYCLE
] if [PDNX•256•t
34 t
Min
100
150
140
5.5
40
40
12
CYCLE
-1
0
5
4
8
2
7
2
100ms
SCYCLE
Version 1.4 Dec. 2003
200.0
Max
10.0
200
100
32
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Direct RDRAM
] < [PDNXA•64•t
CYCLE
ms/t
t
t
t
t
t
t
t
t
t
t
t
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
Unit
ms
ms
ms
ms
ms
ns
ns
ns
ns
CYCLE
values.
SCY-
Figure(s)
Figure 59
Figure 59
Figure 50
Figure 60
Figure 50
Figure 50
Figure 49
Figure 54
Figure 54
Figure 50
Figure 49
Figure 48
Figure 47
Figure 52
Figure 53
Figure 54
Figure 55
Figure 55
Figure 55
Figure 55
page 38
™