w6692 Winbond Electronics Corp America, w6692 Datasheet - Page 54

• Manufacturer Part Number: w6692
• Description: Pci Bus Isdn S/t-controller
• Manufacturer: Winbond Electronics Corp America

bytes of data can be written.
8.1.3 D_ch command register
Value after reset: 00H
RACK
the interrupt.
RRST
STT1
XMS
controller.
XME Transmit Message End
closing flag after the data transmission.
Note: If the frame
XRST Transmitter Reset
pattern (which is 1's) immediately. This command also results in a transmit FIFO ready condition.
8.1.4 D_ch Mode Register D_MODE
Value after reset : 00H
RACK
After an D_XFR interrupt, up to 64 bytes of data can be written into this FIFO for transmission. At the first time, up to 128
Setting this bit indicates the end of frame transmission.. The D_ch HDLC controller automatically appends the CRC and the
The D_XFIFO has a length of 128 bytes.
After a D_RMR or D_RME interrupt, the processor must read out the data in D_RFIFO and then sets this bit to acknowledge
Setting this bit resets the D_ch HDLC receiver and clears the D_RFIFO data.
The timer 1 is started when this bit is set to one. The timer is stopped when it expires or by a write of the TIMR1 register.
Setting this bit resets the D_ch HDLC transmitter and clears the D_XFIFO. The transmitter will send inter frame time fill
A read of this register returns the last written value.
Setting this bit will start or continue the transmission of a frame. The opening flag is automatically added by the HDLC
7
Transmit Message Start/Continue
Start Timer 1
Receiver Reset
Receive Acknowledge
RRST
6
64 bytes, XME plus XMS commands must be issued at the same time.
5
STT1
4
XMS
D_CMDR
3
Read/Write Address 0CH/03H
2
-54 -
Read/Write Address 08H/02H
XME
1
XRST
0
W6692 PCI ISDN S/T-Controller
Publication Release Date:
Preliminary Data Sheet
Sep 30, 1999
Revision 0.9