w6692 Winbond Electronics Corp America, w6692 Datasheet - Page 59

• Manufacturer Part Number: w6692
• Description: Pci Bus Isdn S/t-controller
• Manufacturer: Winbond Electronics Corp America

transmission of closing flag.
DRDY
8.1.11 D_ch Receive Status Register
Value after reset: 20H
RDOV
condition will set both the status and interrupt bits. It is recommended that software must read the RDOV bit after reading data
from D_RFIFO at RMR or RME interrupt. The software must abort the data and issue a RRST command to reset the receiver if
RDOV = 1. The frame overflow condition will not set this bit.
CRCE
RMB
the receiver.
Note: Normally D_RSTA register should be read by the microprocessor after a D_RME interrupt. The contents of D_RSTA are
valid only after a D_RME interrupt and remain valid until the frame is acknowledged via a RACK bit.
8.1.12 D_ch SAPI Address Mask D_SAM
Value after reset: 00H
A "1" indicates that the D_RFIFO is overflow. The incoming data will overwrite data in the receive FIFO. The data overflow
This bit indicates the status of layer 1 D channel.
This bit indicates the result of frame CRC check:
A "1" means that a sequence of seven 1's was received and the frame is aborted. Software must issue RRST command to reset
This bit indicates the D_HDLC transmitter is busy. The XBZ bit is active from the transmission of opening flag to the
0: The layer 1 D channel is not ready. No transmission is allowed.
1: The layer 1 D channel is ready. Layer 2 can transmit data to layer 1.
0: CRC correct
1: CRC error
7
7
Receive Message Aborted
CRC Error
D Channel Ready
Receive Data Overflow
RDOV
6
6
CRCE
5
5
RMB
4
4
3
3
D_RSTA
2
2
-59 -
Read/Write Address 2CH/0BH
1
1
Read
0
0
W6692 PCI ISDN S/T-Controller
Publication Release Date:
Address 28H/0AH
Preliminary Data Sheet
Sep 30, 1999
Revision 0.9