w6692 Winbond Electronics Corp America, w6692 Datasheet - Page 65

• Manufacturer Part Number: w6692
• Description: Pci Bus Isdn S/t-controller
• Manufacturer: Winbond Electronics Corp America

XIND1
XIND0
MSYN
bit patterns.
SCIE
S1-4
bits are double buffered.
8.1.26 S/Q Channel Transmit Register
Value after reset: 0FH
SCIE
Q1-4
8.1.27 Peripheral Control Register
Value after reset: 00H
OE5
When this bit is "1", a multiframe synchronization is achived, i.e the S/T receiver has synchronized to the received F
This bit reflects the current level of XINTIN1 pin.
This bit reflects the current level of XINTIN0 pin.
This bit reflects the bit written in the SQX register.
These are the S bits received in NT to TE direction in frames 1, 6, 11 and 16. S1 is in frame 1, S2 is in frame 6 etc. This four
This bit is used to enable/disable the generation of CIR:SCC status bit and interrupt.
These are the transmitted Q channels in F
A read to this register returns the previous written value.
Used when XMODE=0 only.
OE5
0 : Status bit and interrupt are disabled.
1 : Status bit and interrupt are enabled.
7
7
Received S Bits
Direction Control for IO10
Transmitted Q Bits
S Channel Change Interrupt Enable
S Channel Change Interrupt Enable
Multiframe Synchronization
XINTIN1 Data
XINTIN0 Data
OE4
6
6
OE3
5
5
SCIE
OE2
4
4
A
bit positions in frames 1, 6, 11 and 16. Q1 is in frame 1 and Q2 is in frame 6 etc.
OE1
Q1
3
3
SQX
PCTL
OE0
Q2
2
2
-65 -
XMODE
Q3
Read/Write
Read/Write
1
1
PXC
Q4
W6692 PCI ISDN S/T-Controller
0
0
Publication Release Date:
Preliminary Data Sheet
Address 64H/19H
Address 68H/1AH
Sep 30, 1999
Revision 0.9
A
and M