emc643sp16ak Emlsi Inc., emc643sp16ak Datasheet - Page 14

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emc643sp16ak

Manufacturer Part Number
emc643sp16ak
Description
4mx16 Bit Cellularram Ad-mux
Manufacturer
Emlsi Inc.
Datasheet
Figure 7: Refresh Collision During Variable-Latency READ Operation
Note: Non-default BCR settings for refresh collision during variable-latency READ operation:
Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
A/DQ[15:0]
LB#/UB#
A[21:16]
ADV#
WAIT
WE#
CE#
OE#
CLK
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
OH
OH
IH
IH
OL
OL
IL
IH
IL
IH
IH
IH
IL
IL
IL
IL
IL
Additional WAIT states inserted to allow refresh completion.
High-Z
Address
Address
Valid
Valid
V
V
OH
OL
14
D0
D1
4Mx16 CellularRAM AD-MUX
Don’t Care
D2
EMC643SP16AK
D3
Undefined

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