emc643sp16ak Emlsi Inc., emc643sp16ak Datasheet - Page 35

• Manufacturer Part Number: emc643sp16ak
• Description: 4mx16 Bit Cellularram Ad-mux
• Manufacturer: Emlsi Inc.

Table 16: Burst WRITE Cycle Timing Requirements
Note:
1. t
2. A refresh opportunity must be provided every t
3. The High-Z timings measure a 100mV transition from either V
Address and ADV# LOW setup time
to WE# LOW
Address HOLD from ADV# HIGH(fixed latency)
CE# HIGH between subsequent burst or mixed
mode operations
Maximum CE# pulse width
Clock period
CE# setup to CLK active edge
Hold time from active CLK edge
Chip disable to WAIT High-Z output
CLK rise or fall time
Clock to WAIT valid
CLK HIGH or LOW time
Setup time to activate CLK edge
Parameter
HIGH, or b) CE# HIGH for longer than 15ns.
AS
required if t
CSP
> 20ns.
CEM
. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE#
Symbol
t
t
t
t
t
CBPH
t
t
KHKL
KHTL
t
CEM
t
t
t
t
AVH
CLK
CSP
HD
AS
HZ
KP
SP
OH
or V
OL
toward VccQ/2.
Min
7.5
2.5
1.5
0
2
5
3
2
133MHz
35
Max
1.2
5.5
4
7
9.62
Min
0
2
5
3
2
3
3
104MHz
Max
1.6
4
7
7
4Mx16 CellularRAM AD-MUX
EMC643SP16AK
Min
12
0
2
6
4
2
4
3
83MHZ
Max
1.8
4
7
9
Unit
ns
ns
ns
µ
ns
ns
ns
ns
ns
ns
ns
ns
s
Notes
1
2
2
3