emc643sp16ak Emlsi Inc., emc643sp16ak Datasheet - Page 29

• Manufacturer Part Number: emc643sp16ak
• Description: 4mx16 Bit Cellularram Ad-mux
• Manufacturer: Emlsi Inc.

Partial Array Refresh (RCR[2:0] Default = Full Array Refresh)
The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by
refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter
array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address
map(See Table 7 and Table 8).
Table 7: Address Patterns for PAR (RCR[4] = 1)
Device Identification Register
The DIDR provides information on the device manufacturer, CellularRAM generation, and the specific device configuration. Table 8
describes the bit fields in the DIDR. This register is read-only. The DIDR is accessed with CRE HIGH and A[19:18] = 01b, or through the
register access software sequence with A/DQ = 0002h on the third cycle.
Table 8: Device Identification Register Mapping
Field name
Bit Field
RCR[2]
Options
0
0
0
0
1
1
1
1
128 words
RCR[1]
Length
0
0
1
1
0
0
1
1
Row Length
DIDR[15]
RCR[0]
Setting
Bit
0b
0
1
0
1
0
1
0
1
Version
2nd
One-quarter of die
One-quarter of die
One-eighth of die
One-eighth of die
Device version
DIDR[14:11]
Active Section
One-half of die
One-half die
None of die
Full Die
Setting
0001b
Bit
Density
64Mb
29
Device density
000000h-3FFFFFh
000000h-1FFFFFh
000000h-0FFFFFh
000000h-07FFFFh
200000h-3FFFFFh
300000h-3FFFFFh
380000h-3FFFFFh
DIDR[10:8]
Address Space
0
Setting
010b
Bit
Generation
CellularRAM generation
CR 1.5
DIDR[7:5]
4Mx16 CellularRAM AD-MUX
4 Meg x 16
2 Meg x 16
1 Meg x 16
0 Meg x 16
2 Meg x 16
1 Meg x 16
512 K x 16
512 K x 16
EMC643SP16AK
Size
Setting
010b
Bit
EMLSI
Vendor
DIDR[4:0]
Vendor ID
Density
64Mb
32Mb
16Mb
32Mb
16Mb
8Mb
0Mb
8Mb
01010b
Setting
Bit