hsd2m64b2 ETC-unknow, hsd2m64b2 Datasheet - Page 6

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hsd2m64b2

Manufacturer Part Number
hsd2m64b2
Description
Synchronous Dram Module 16mbyte 2mx64-bit , So-dimm, 4banks, Ref., 3.3v
Manufacturer
ETC-unknow
Datasheet
HANBit
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
Operating current
(Burst mode)
Refresh current
Self refresh current
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS(V
AC OPERATING TEST CONDITIONS
(vcc = 3.3V ± 0.3V, TA = 0 to 70°C)
URL:www.hbe.co.kr
REV.1.0 (August.2002)
AC Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
PARAMETER
I
I
I
CC2
CC3
I
CC3
I
CC3
CC3
I
I
I
CC4
CC5
CC6
NS
NS
PS
P
N
CKE
Input signals are stable
CKE
CKE&CLK
t
CKE V
CS* V
Input signals are changed
one time during 20ns
CKE VIH(min)
CLK VIL(max), t
Input signals are stable
I
Page burst
4Banks Activated
t
t
CC
O
CCD
RC
CLK
= 0 mA
=
= 2CLKs
t
RC
IH
V
V
IH
V
(min)
(min), t
IH
IL
(min),
CKE
IL
(max), t
(min)
(max), t
IH
V
/V
IL
6
(max)
IL
0.2V
CC
=V
CC
CC
=10ns
=10ns
DDQ
CC
=
=
/V
SSQ
).
See Fig. 2
tr/tf = 1/1
2.4/0.4
Value
1.4
1.4
150
160
450
10
30
20
3
3
2
130
150
HANBit Electronics Co.,Ltd.
HSD2M64B2
mA
mA
mA
mA
mA
mA
UNIT
V
V
Ns
V
2
3
5

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