hsd2m64b2 ETC-unknow, hsd2m64b2 Datasheet - Page 9

• Manufacturer Part Number: hsd2m64b2
• Description: Synchronous Dram Module 16mbyte 2mx64-bit , So-dimm, 4banks, Ref., 3.3v
• Manufacturer: ETC-unknow

HANBit
SIMPLIFIED TRUTH TABLE
Register
Refresh
Bank active & row addr.
Read &
column
address
Write &
column
address
Burst Stop
Precharg
e
Clock suspend or
active power down
Precharge
down mode
DQM
No operation command
Notes :
1. OP Code : Operand code
2. MRS can be issued only at all banks precharge state.
3. Auto refresh functions are as same as CBR refresh of DRAM.
4. BA0 ~ BA1 : Bank select addresses.
5. During burst read or write with auto precharge, new read/write command can not be issued.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
URL:www.hbe.co.kr
REV.1.0 (August.2002)
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
A new command can be issued after 2 CLK cycles of MRS.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2
COMMAND
Mode register set
Auto refresh
Self
refres
h
Auto
disable
Auto
disable
Auto
disable
Auto
disable
Bank selection
All banks
power
precharge
precharge
precharge
precharge
Entry
Exit
Entry
Exit
Entry
Exit
CKE
n-1
H
H
H
H
H
H
H
H
H
H
H
L
L
L
CKE
N
X
H
H
X
X
X
X
X
H
H
X
L
L
L
/C
S
H
H
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
/R
A
S
H
X
H
H
X
V
X
X
H
X
V
L
L
L
L
L
9
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
H
X
/C
A
S
H
X
H
H
H
X
V
X
X
H
X
V
L
L
L
L
/W
E
H
H
X
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
D
Q
M
X
X
X
X
X
X
X
X
X
X
X
X
V
X
)
BA
0,1
V
V
V
V
X
HANBit Electronics Co.,Ltd.
A10/
OP code
AP
H
H
L
L
H
L
Row address
HSD2M64B2
X
X
X
X
X
X
X
(A0 ~ A9)
(A0 ~ A9)
Address
Address
Column
Column
A9~A0
X
NOTE
1,2
4,5
4,5
3
3
3
3
4
4
6
7