hsd2m64b2 ETC-unknow, hsd2m64b2 Datasheet - Page 7

• Manufacturer Part Number: hsd2m64b2
• Description: Synchronous Dram Module 16mbyte 2mx64-bit , So-dimm, 4banks, Ref., 3.3v
• Manufacturer: ETC-unknow

HANBit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
URL:www.hbe.co.kr
REV.1.0 (August.2002)
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
then rounding off to the next higher integer.
.
D
Number of valid output data
OUT
870
PARAMETER
(Fig. 1) DC output load circuit
+3.3V
1200
50pF*
V
V
OH
OL
CAS latency=3
CAS latency=2
(DC) = 0.4V, I
(DC) = 2.4V, I
SYMBOL
t
t
t
t
t
t
t
RAS
t
t
RRD
RAS
tRC
RDL
CDL
CCD
BDL
RP
RP
(min)
(min)
(min)
(max)
(min)
(min)
(min)
(min)
(min)
(min)
OL
OH
7
= 2mA
= -2mA
D
OUT
-8
2
3
3
6
9
VERSION
(Fig. 2) AC output load circuit
100
2
1
1
1
2
1
Z0=50
-10
2
2
2
5
7
HANBit Electronics Co.,Ltd.
HSD2M64B2
V
tt
=1.4V
50
50pF
UNIT
CLK
CLK
CLK
CLK
ea
ns
ns
ns
ns
ns
ns
NOTE
2.5
1
1
1
1
1
2
2
3
4