s5935qrc Applied Micro Circuits Corporation (AMCC), s5935qrc Datasheet - Page 130

• Manufacturer Part Number: s5935qrc
• Description: Pci Product
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

S5935 – PCI Product
Mailbox operations for the Add-On interface are functionally identical. The following sequences are suggested for
Add-On mailbox operations using status polling (interrupts disabled):
Mailbox Interrupts
Although polling status is useful, in some cases, polling requires continuous actions by the processor reading or
writing the mailbox. Mailbox interrupt capabilities are provided to avoid much of the processor overhead required
by continuously polling status bits.
The Add-On and PCI interface can each generate interrupts on an incoming mailbox condition and/or an outgoing
mailbox condition. These can be individually enabled/disabled. A specific byte in one incoming mailbox and one
outgoing mailbox is identified to generate the interrupt(s). The tasks required to setup mailbox interrupts are shown
below:
130
Reading an Add-On Incoming Mailbox:
Writing an Add-On Outgoing Mailbox:
Enabling PCI mailbox interrupts:
2. Read Mailbox(es). Read the mailbox bytes which AMBEF indicates are full. This automatically resets the status bits in
1. Check Mailbox Status. Read the mailbox status register to determine if information previously written to the mailbox has
2. Write Mailbox(es). Write to the outgoing mailbox byte(s).
1. Enable PCI outgoing mailbox interrupts. A specific byte within one of the outgoing mailboxes is identified to assert
2. Enable PCI incoming mailbox interrupts. A specific byte within one of the incoming mailboxes is identified to assert
1. Check Mailbox Status. Read the mailbox status register to determine if any information has been passed from the PCI interface.
INTCSR
INTCSR
INTCSR
INTCSR
INTCSR
INTCSR
AMBEF
AMBEF
AOMBx
AIMBx
the AMBEF and MBEF registers.
been read by the PCI interface. Writes to full mailbox bytes overwrite data currently in the mailbox (if not already read
by the PCI interface). Repeat until the byte(s) to be written are empty.
INTA# when read by the Add-On interface.
INTA# when written by the Add-On interface.
DS1527
Bits 15:0
Bits 31:0
Bits 31:16
Bits 31:0
Bit 4
Bits 3:2
Bits 1:0
Bit 12
Bits 11:10
Bits 9:8
If a bit is set, valid data is contained in the corre-
sponding mailbox byte.
Mailbox data.
If a bit is set, valid data is contained in the corre-
sponding mailbox byte and has not been read by
the PCI bus.
Mailbox data.
Enable outgoing mailbox interrupts
Identify mailbox to generate interrupt
Identify mailbox byte to generate interrupt
Enable incoming mailbox interrupts
Identify mailbox to generate interrupt
Identify mailbox byte to generate interrupt
Revision 1.02 – June 27, 2006
AMCC Confidential and Proprietary
Data Book