s5935qrc Applied Micro Circuits Corporation (AMCC), s5935qrc Datasheet - Page 63

• Manufacturer Part Number: s5935qrc
• Description: Pci Product
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

S5935 – PCI Product
PCI CONTROLLED BUS MASTER WRITE
TRANSFER COUNT REGISTER (MWTC)
Figure 25. PCI Controlled Bus Master Write Transfer Count Register
AMCC Confidential and Proprietary
Register Name
PCI Address Offset
Power-up value
Attribute
Size
31
Master Write Transfer Count
28h
00000000h
Read/Write
32 bits
00
26
25
The master write transfer count register is used to con-
vey to the S5935 controller the actual number of bytes
that are to be transferred. The value in this register is
decremented with each bus master PCI write opera-
tion until the transfer count reaches zero.
Upon reaching zero, the transfer operation ceases and
an interrupt may be optionally generated to either the
PCI or Add-On bus interface. Transfers which are not
whole multiples of DWORDs in size result in a partial
word ending cycle. This partial word ending cycle is
possible since all bus master transfers for this control-
ler are required to begin on a DWORD boundary.
Under certain circumstances, MWTC can be accessed
from the Add-On bus instead of the PCI bus. See Add-
On Initiated Bus Mastering.
Revision 1.02 – June 27, 2006
0
Bit
Value
Transfer Count
in Bytes (R/W)
Reserved = O's (RO)
Data Book
DS1527
63