s5935qrc Applied Micro Circuits Corporation (AMCC), s5935qrc Datasheet - Page 76

• Manufacturer Part Number: s5935qrc
• Description: Pci Product
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

S5935 – PCI Product
ADD-ON BUS OPERATION REGISTERS
The Add-On bus interface provides access to 18
DWORDs (72 bytes) of data, control and status infor-
mation. All of these locations are accessed by
asserting the Add-On bus chip select pin (SELECT#)
in conjunction with either the read or write control
strobes (signal pin RD# or WR#). Access to the FIFO
can also be achieved through use of the dedicated
pins, RDFIFO# and WRFIFO#. The dedicated pins for
control of the FIFO are provided to optionally imple-
ment Direct Memory Access (DMA) on the Add-On
bus, or to connect with an external FIFO.
This register group represents the primary method for
communication between the Add-On and PCI buses
Table 34. Operation Registers — Add-On Interface
1. See Add-On Initiated Bus Mastering.
76
Address
DS1527
0Ch
1Ch
2Ch
3Ch
5Ch
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
38h
58h
Abbreviation
AGCSTS
AOMB1
AOMB2
AOMB3
AOMB4
MWAR
MWTC
MRAR
AMBEF
MRTC
AIMB1
AIMB2
AIMB3
AIMB4
AFIFO
APTA
APTD
AINT
1
1
1
1
Add-On Incoming Mailbox Register #1
Add-On Incoming Mailbox Register #2
Add-On Incoming Mailbox Register #3
Add-On Incoming Mailbox Register #4
Add-On Outgoing Mailbox Register #1
Add-On Outgoing Mailbox Register #2
Add-On Outgoing Mailbox Register #3
Add-On Outgoing Mailbox Register #4
Add-On FIFO port
Bus Master Write Address Register
Add-On Pass-Through Address
Add-On Pass-Through Data
Bus Master Read Address Register
Add-On Mailbox Empty/Full Status
Add-On Interrupt control
Add-On General Control and Status Register
Bus Master Write Transfer Count
Bus Master Read Transfer Count
as viewed by the Add-On. The flexibility of this
arrangement allows a number of user-defined soft-
ware protocols to be built. For example, data, software
assigned commands, and command parameters can
be exchanged between the PCI and Add-On buses
using either the mailboxes or FIFOs with or without
handshaking interrupts. The register structure is very
similar to that of the PCI operation register set. The
major difference between the PCI bus and Add-On
bus register complement are the absence of bus mas-
ter control registers (4) on the Add-On side and the
addition of two “pass-through” registers. Table 1 lists
the Add-On interface registers.
Register Name
Revision 1.02 – June 27, 2006
AMCC Confidential and Proprietary
Data Book