s5935qrc Applied Micro Circuits Corporation (AMCC), s5935qrc Datasheet - Page 53

• Manufacturer Part Number: s5935qrc
• Description: Pci Product
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

S5935 – PCI Product
EXPANSION ROM BASE ADDRESS
REGISTER (XROM)
Figure 19. Expansion ROM Base Address Register
Table 28. Expansion ROM Base Address Register
AMCC Confidential and Proprietary
Register Name
Address Offset
Power-up value
Boot-load
Attribute
Size
31:11
10:1
Bit
31
0
Expansion ROM Base Address Location. These bits are used to position the decoded region in memory space. Only
bits which return a 1 after being written as 1 are usable for this purpose. These bits are individually enabled by the
contents sourced from the external boot memory (EPROM or nvRAM). The desired size for the ROM memory is
determined by writing all ones to this register and then reading back the contents. The number of bits returned as
zeros, in order from least significant to most significant bit, indicates the size of the expansion ROM. This controller
limits the expansion ROM area to 64K bytes. The allowable returned values after all ones are written to this register
are shown in Table 26.
Reserved. All zeros.
Address Decode Enable. The Expansion ROM address decoder is enabled or disabled with this bit. When this bit is
set, the decoder is enabled; when this bit is zero, the decoder is disabled. It is required that the PCI command regis-
ter also have the memory decode enabled for this bit to have an effect.
Expansion ROM Base Address
bits 31:11, bit 0 Read/Write; bits 10:1
Read Only
30h
00000000h
External nvRAM offset 70h
32 bits
11
10
Description
The expansion base address ROM register provides a
mechanism for assigning a space within physical
memory for an expansion ROM. Access from the PCI
bus to the memory space defined by this register will
cause one or more accesses to the S5935 controllers’
external BIOS ROM (or nvRAM) interface. Since PCI
bus accesses to the ROM may be 32 bits wide,
repeated operations to the ROM are generated by the
S5935 and the wider data is assembled internal to the
S5935 controller and then transferred to the PCI bus
by the S5935.
0
1
Revision 1.02 – June 27, 2006
0
0
Bit
Value
Address Decode
Enable (RW)
Reserved (RO)
Programmable (R/W)
0=Disabled
1=Enabled
Data Book
DS1527
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