s5935qrc Applied Micro Circuits Corporation (AMCC), s5935qrc Datasheet - Page 77

• Manufacturer Part Number: s5935qrc
• Description: Pci Product
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

S5935 – PCI Product
ADD-ON INCOMING MAILBOX REGISTERS (AIMBX)
ADD-ON OUTGOING MAILBOX REGISTERS (AOMBX)
ADD-ON FIFO REGISTER PORT (AFIFO)
AMCC Confidential and Proprietary
Register Names
Add-On Address Offset
Power-up value
Attribute
Size
Register Names
Add-On Address Offset
Power-up value
Attribute
Size
Register Name
Add-On Address
Offset
Power-up value
Attribute
Size
Add-On FIFO Port
20h
Read/Write
32 bits
XXXXXXXXh
Add-On Incoming Mailboxes
1-4
00h, 04h, 08h, 0Ch
XXXXXXXXh
Read Only
Add-On Outgoing Mailboxes
1-4
10h, 14h, 18h, 1Ch
XXXXXXXXh
Read/Write
32 bits
32 bits
This location provides access to the bidirectional FIFO. Separate registers are
involved when reading and writing to this location. Accordingly, it is not possible
to read what was written to this location. The sequence of filling and emptying
this FIFO is established by the PCI interface interrupt control and Status Regis-
ter.
The FIFO’s fullness may be observed by reading the master control/status regis-
ter or AGCSTS register Additionally, two signal pins are provided which reveal
whether data is available (RDEMPTY) or space to write into the FIFO is available
(WRFULL). These signals may be used to interface with user supplied DMA
logic. Caution must be exercised when using these flags for FIFO transfers
involving 64 bit endian conversion since the FIFO must operate on DWORD
pairs.
These four DWORD registers provide a method for receiving
data, commands, or command parameters from the PCI
interface. Add-On read operations to these registers may be
in any width (byte, word, or DWORD). These registers are
read-only. Writes to this address space have no effect.
Reading from one of these registers can optionally cause a
PCI bus interrupt (if desired) when the PCI interrupt control/
status register is properly configured.
These four DWORD registers provide a method for sending
data, commands, or command parameters or status to the
PCI interface. Add-On write operations to these registers
may be in any width (byte, word, or DWORD). These regis-
ters may also be read. Writing to one of these registers can
optionally cause a PCI bus interrupt (if desired) when the
PCI interrupt control/status register is properly configured.
Mailbox 4, byte 3 only exists as device pins on the S5935
device when used with a serial nonvolatile memory. This
byte is not available if a byte-wide nv memory is used.
Revision 1.02 – June 27, 2006
Data Book
DS1527
77