s5935qrc Applied Micro Circuits Corporation (AMCC), s5935qrc Datasheet - Page 147

• Manufacturer Part Number: s5935qrc
• Description: Pci Product
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

S5935 – PCI Product
The Add-On General Control/Status (AGCSTS) Add-
On Operation Register allows an Add-On CPU to mon-
itor FIFO activity and control FIFO operation. Reset
controls allow the PCI to Add-On FIFO and Add-On to
PCI FIFO flags to be reset (individually). Status bits
indicate if the PCI to Add-On FIFO is empty, has four
or more open spaces, or is full. Status bits also indi-
cate if the Add-On to PCI is empty, has four or more
full spaces or is full. FIFO bus mastering status may
be monitored through this register, but all bus master
configuration is through the MCSR PCI Operation
Register.
PCI Initiated FIFO Bus Mastering Setup
For PCI initiated bus mastering, the PCI host sets up
the S5935 to perform bus master transfers. The follow-
ing tasks must be completed to setup FIFO bus
mastering:
AMCC Confidential and Proprietary
1. Define interrupt capabilities. The PCI to Add-On
INTCSR
INTCSR
2. Reset FIFO flags. This may not be necessary, but
MCSR
MCSR
and/or Add-On to PCI FIFO can generate a PCI
interrupt to the host when the transfer count
reaches zero.
if the state of the FIFO flags is not known, they
should be initialized.
Bit 26
Bit 25
Bit 15
Bit 14
Enable Interrupt on read transfer
count equal zero
Enable Interrupt on write transfer
count equal zero
Reset Add-On to PCI FIFO flags
Reset PCI to Add-On FIFO flags
MWAR
MRAR
3. Define FIFO management scheme. These bits
MCSR
MCSR
4. Define PCI to Add-On and Add-On to PCI FIFO
MCSR
MCSR
5. Define
6. Define transfer byte counts. These registers are
MWTC
MRTC
define what FIFO condition must exist for the PCI
bus request (REQ#) to be asserted by the S5935.
priority. These bits determine which FIFO has pri-
ority if both meet the defined condition to request
the PCI bus. If these bits are the same, priority
alternates, with read accesses occurring first.
These registers are written with the first address
that is to be accessed by the S5935. These
address registers are updated after each access
to indicate the next address to be accessed.
Transfers must start on DWORD boundaries.
written with the number of bytes to be transferred.
The transfer count does not have to be a multiple
of four bytes. These registers are updated after
each transfer to reflect the number of bytes
remaining to be transferred.
Bit 13
Bit 12
Bit 9
Bit 8
All
All
transfer
All
All
PCI to Add-On FIFO management
scheme
Add-On to PCI FIFO management
scheme
Read vs. write priority
Write vs. read priority
Bus master write address
Bus master read address
Write transfer byte count
Read transfer byte count
Revision 1.02 – June 27, 2006
source/destination
Data Book
DS1527
address.
147