gvt71256zb18 ETC-unknow, gvt71256zb18 Datasheet - Page 10

• Manufacturer Part Number: gvt71256zb18
• Description: 256k Flow-through Sram
• Manufacturer: ETC-unknow

Note:
1. Q(A
2. CE2# timing transitions are identical to the CE# signal. For example, when CE# is LOW on this waveform, CE2#
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD# LOW.
4. R/W# is “Don’t Care” when the SRAM is bursting (ADV/LD# sampled HIGH). The nature of the burst access
July 23, 1998
Rev. 7/98
GALVANTECH
BWa#, BWb#
(See Note)
address A
address bits SA0 and SA1 are advancing for the four word burst in the sequence defined by the state of the
MODE input.
is LOW. CE2 timing transitions are identical but inverted to the CE# signal. For example, when CE# is LOW on
this waveform, CE2 is HIGH.
(Read or Write) is fixed by the state of the R/W signal when new address and control are loaded into the SRAM.
ADDRESS
ADV/LD#
1
CKE#
) represents the first output from the external address A
R/W#
CLK
OE#
CE#
DQ
2
; Q(A
A
1
2
+1) represents the next output data in the burst sequence of the base address A
Read
t
t
t
t
t
t
KQLZ
S
S
S
S
S
Q(A
1
)
A
2
t
KQ
Read
t
t
t
t
t
H
H
H
H
H
Q(A
, INC.
2
)
t
t
KQX
KC
Q(A
READ TIMING
t
KL
2
+1)
256K X 18 FLOW-THROUGH ZBL SRAM
10
Q(A
2
+2)
1
. Q(A
BURST READ
t
KH
2
) represents the first output from the external
(CKE# HIGH , eliminates
current L-H clock edge)
Galvantech, Inc. reserves the right to change products or specifications without notice.
Q(A
2
+3)
(Burst Wraps around
to initial state)
GVT71256ZB18
Q(A
2
)
t
KQHZ
2
, etc. where
Deselect