gvt71256zb18 ETC-unknow, gvt71256zb18 Datasheet - Page 3

• Manufacturer Part Number: gvt71256zb18
• Description: 256k Flow-through Sram
• Manufacturer: ETC-unknow

PIN DESCRIPTIONS
July 23, 1998
Rev. 7/98
GALVANTECH
32, 33, 34, 35, 44,
45, 46, 47, 48, 49,
50, 80, 81, 82, 99,
TQFP PINS
100
37,
36,
93,
94
87
88
89
SYMBOL
BWa#,
BWb#,
CKE#
R/W#
SA0,
SA1,
CLK
SA
VCCQ
VCCQ
VCCQ
VCCQ
DQPb
VCC
VCC
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
TYPE
Input-
Input-
Input-
Input-
Input-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
8
9
100 99
, INC.
31
32
PIN ASSIGNMENT (Top View)
98
33
Synchronous Address Inputs: The address register is triggered by a combination of the
rising edge of CLK, ADV/LD# LOW, CKE# LOW and true chip enables. SA0 and SA1 are
the two least significant bits of the address field and set the internal burst counter if burst
cycle is initiated.
Synchronous Byte Write Enables: Each 9-bit byte has its own active low byte write enable.
On load write cycles (when R/W# and ADV/LD# are sampled LOW), the appropriate byte
write signal (BWx#) must be valid. The byte write signal must also be valid on each cycle of
a burst write. Byte write signals are ignored when R/W# is sampled high. The appropriate
byte(s) of data are written into the device one cycle later. BWa# controls DQa and DQPa
pins; BWb# controls DQb and DQPb pins. BWx# can all be tied LOW if always doing write
to the entire 18-bit word.
Synchronous Clock Enable Input: When CKE# is sampled HIGH, all other synchronous
inputs, including clock are ignored and outputs remain unchanged. The effect of CKE#
sampled HIGH on the device outputs is as if the low to high clock transition did not occur.
For normal operation, CKE# must be sampled LOW at rising edge of clock.
Read Write: R/W# signal is a synchronous input that identifies whether the current loaded
cycle and the subsequent burst cycles initiated by ADV/LD# is a Read or Write operation.
The data bus activity for the current cycle takes place one clock cycle later.
Clock: This is the clock input to GVT71256ZB18. Except for OE#, ZZ and MODE, all timing
references for the device are made with respect to the rising edge of CLK.
97
34
96
35
95
36
94
37
100-pin TQFP
93
38
92
39
256K X 18 FLOW-THROUGH ZBL SRAM
91
40
90
41
3
89
42
88
43
87
44
86
45
85
46
84
47
83
48
DESCRIPTION
82
49
81
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Galvantech, Inc. reserves the right to change products or specifications without notice.
NC
SA
NC
NC
VCCQ
VSS
DQPa
DQa
DQa
VSS
VCCQ
DQa
DQa
VSS
VSS
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
NC
NC
VSS
VCCQ
NC
NC
NC
GVT71256ZB18