gvt71256zb18 ETC-unknow, gvt71256zb18 Datasheet - Page 6

• Manufacturer Part Number: gvt71256zb18
• Description: 256k Flow-through Sram
• Manufacturer: ETC-unknow

TRUTH TABLE
Note:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. CONTINUE BURST cycles, whether READ or WRITE, use the same control signals. The type of cycle performed, READ
11. DUMMY READ and ABORT WRITE cycles can be entered to setup subsequent READ or WRITE cycles or to increment
12. When an IGNORE CLOCK EDGE cycle enters, the output data (Q) will remain the same if the previous cycle is READ
July 23, 1998
Rev. 7/98
DESELECT CYCLE
CONTINUE
DESELECT/NOP
READ CYCLE
(BEGIN BURST)
READ CYCLE
(CONTINUE BURST)
DUMMY READ
(BEGIN BURST)
DUMMY READ
(CONTINUE BURST)
WRITE CYCLE
(BEGIN BURST)
WRITE CYCLE
(CONTINUE BURST)
ABORT WRITE
(BEGIN BURST)
ABORT WRITE
(CONTINUE BURST)
IGNORE CLOCK
EDGE /NOP
GALVANTECH
OPERATION
L means logic LOW. H means logic HIGH. X means “Don’t Care.”
[BWa#*BWb#] equals LOW. BWx# = H means [BWa#*BWb#] equals HIGH.
CE# equals H means CE# and CE2# are LOW along with CE2 being HIGH. CE# equals L means CE# or CE2# is HIGH or CE2 is LOW.
CE# equals X means CE#, CE2# and CE2 are “Don’t Care.”
BWa# enables WRITE to byte “a” (DQa and DQPa pins). BWb# enables WRITE to byte “b” (DQb and DQPb pins).
The device is not in SNOOZE MODE, i.e. the ZZ pin is LOW.
During SNOOZE MODE, the ZZ pin is HIGH and all the address pins and control pins are “
can only be entered 1 cycle after the WRITE cycle, otherwise the WRITE cycle may not be completed.
All inputs, except OE#, ZZ and MODE pins, must meet setup time and hold time specification against the clock (CLK)
LOW-to-HIGH transition edge.
OE# may be tied to LOW for all the operation. This device automatically turns off the output driver during WRITE cycle.
Device outputs are ensured to be in High-Z during device power-up.
This device contains a 2-bit burst counter. The address counter is incremented for all CONTINUE BURST cycles. Address
wraps to the initial address every fourth burst cycle.
or WRITE, depends upon the R/W# control signal at the BEGIN BURST cycle. A CONTINUE DESELECT cycle can only
be entered if a DESELECT cycle is executed first.
the burst counter.
cycle or remain High-Z if the previous cycle is WRITE or DESELECT cycle.
(1-9)
PREVIOUS
DESELECT
WRITE
WRITE
CYCLE
READ
READ
X
X
X
X
X
X
ADDRESS
External
External
External
External
USED
Next
Next
Next
Next
X
X
X
, INC.
R/W#
X
X
H
X
H
X
X
X
X
L
L
ADV/LD#
256K X 18 FLOW-THROUGH ZBL SRAM
H
H
H
H
H
H
L
L
L
L
L
6
High-Z means HIGH IMPEDANCE.
CE#
H
X
X
X
X
X
X
L
L
L
L
CKE#
H
L
L
L
L
L
L
L
L
L
L
Galvantech, Inc. reserves the right to change products or specifications without notice.
BWx#
H
H
X
X
X
X
X
X
X
L
L
Don’t Care.” The SNOOZE MODE
OE#
X
X
X
X
H
H
X
X
X
X
X
GVT71256ZB18
BWx# = L means
(1 cycle later)
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DQ
Q
Q
D
D
-
NOTES
10, 11
10, 11
10
10
11
10
11
12