gvt71256zb18 ETC-unknow, gvt71256zb18 Datasheet - Page 12

• Manufacturer Part Number: gvt71256zb18
• Description: 256k Flow-through Sram
• Manufacturer: ETC-unknow

Note:
1. Q(A
2. CE2# timing transitions are identical to the CE# signal. For example, when CE# is LOW on this waveform, CE2#
3
.
July 23, 1998
Rev. 7/98
DATA Out (Q)
. Individual Byte Write signals (BWx#) must be valid on all write and burst-write cycles. A write cycle is initiated
GALVANTECH
BWa#, BWb#
DATA In (D)
corresponding to address A
is LOW. CE2 timing transitions are identical but inverted to the CE# signal. For example, when CE# is LOW on
this waveform, CE2 is HIGH.
when R/W# signal is sampled LOW when ADV/LD# is sampled LOW. The byte write information comes in one
cycle before the actual data is presented to the SRAM.
(See Note)
ADDRESS
ADV/LD#
1
CKE#
) represents the first output from the external address A
R/W#
CLK
OE#
CE#
A
1
t
KQ
Read
t
t
t
t
t
t
S
S
S
S
S
S
Q(A
1
BW(A
)
A
2.
t
2
KQHZ
2
)
Write
t
t
t
t
t
t
H
H
H
H
H
H
, INC.
D(A
A
3
2
)
READ/WRITE TIMING
t
Read
KQLZ
t
KC
Q(A
t
KL
3
BW(A
)
A
256K X 18 FLOW-THROUGH ZBL SRAM
4
4
)
12
t
KQX
Write
BW(A
D(A
1
A
. D(A
5
4
5
)
t
)
KH
2
) represents the input data to the SRAM
D(A
D(A
A
Galvantech, Inc. reserves the right to change products or specifications without notice.
6
5
5
)
)
Q(A
6
Read
)
A
7
GVT71256ZB18
Q(A
7
A
)
8
Write
D(A
A
9
8
)