gvt71256zb18 ETC-unknow, gvt71256zb18 Datasheet - Page 4

• Manufacturer Part Number: gvt71256zb18
• Description: 256k Flow-through Sram
• Manufacturer: ETC-unknow

PIN DESCRIPTIONS (continued)
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or NC)
LINEAR BURST ADDRESS TABLE (MODE = VSS)
Note:
1.
July 23, 1998
Rev. 7/98
55, 60, 66, 67, 71, 76, 90
5, 10, 14, 17, 21, 26, 40,
4, 11, 20, 27, 54, 61, 70,
1-3, 6, 7, 25, 28-30, 38,
GALVANTECH
57, 75, 78, 79, 83, 84,
39, 42, 43, 51-53, 56,
15, 16, 41, 65, 91
First Address
First Address
Upon completion of the Burst sequence, the counter wraps around to its initial state and continues counting.
68, 69, 72, 73,
58, 59, 62, 63
18, 19, 22, 23
TQFP PINS
(external)
(external)
8, 9, 12, 13
A...A
A...A
A...A
A...A
A...A
A...A
A...A
A...A
98, 92
74, 24
95, 96
97
86
85
31
64
77
00
01
10
00
01
10
11
11
Second Address
Second Address
DQPa, DQPb
CE#, CE2#
SYMBOL
ADV/LD#
MODE
VCCQ
(internal)
(internal)
DQa
DQb
VCC
CE2
OE#
VSS
NC
ZZ
A...A
A...A
A...A
A...A
A...A
A...A
A...A
A...A
01
00
11
10
01
10
11
00
Asynchronous
Synchronous
Synchronous
Synchronous
I/O Supply
Ground
TYPE
Output
Output
Supply
Input-
input-
Input-
Input-
Static
Input-
Input/
Input/
Input
, INC.
-
Third Address
Third Address
(internal)
(internal)
A...A
A...A
A...A
A...A
A...A
A...A
A...A
A...A
Synchronous Active Low Chip Enable: CE# and CE2# are used with CE2 to enable the
GVT71256ZB18. CE# or CE2# sampled HIGH or CE2 sampled LOW, along with ADV/
LD# LOW at the rising edge of clock, initiates a deselect cycle. The data bus will be
HIGH-Z one clock cycle after chip deselect is initiated.
Synchronous Active High Chip enable: CE2 is used with CE# and CE2# to enable the
chip. CE2 has inverted polarity but otherwise is identical to CE# and CE2#.
Asynchronous Output Enable: OE# must be LOW to read data. When OE# is HIGH,
the I/O pins are in high impedance state. OE# does not need to be actively controlled
for read and write cycles. In normal operation, OE# can be tied LOW.
Advance/Load: ADV/LD# is a synchronous input that is used to load the internal
registers with new address and control signals when it is sampled LOW at the rising
edge of clock with the chip is selected. When ADV/LD# is sampled HIGH, then the
internal burst counter is advanced for any burst that was in progress. The external
addresses and R/W# are ignored when ADV/LD# is sampled HIGH.
Burst Mode: When MODE is HIGH or NC, the interleaved burst sequence is selected.
When MODE is LOW, the linear burst sequence is selected. MODE is a static DC input.
Snooze Enable: This active HIGH input puts the device in low power consumption
standby mode. For normal operation, this input has to be either LOW or NC.
Data Inputs/Outputs: Both the data input path and data output path are registered and
triggered by the rising edge of CLK. Byte “a” is DQa pins; Byte “b” is DQb pins.
Parity Inputs/Outputs: Both the data input path and data output path are registered and
triggered by the rising edge of CLK. DQPa is parity bit for Byte “a”; DQPb is parity bit
for Byte “b”.
Power Supply: +3.3V -5% and +5%.
Ground: GND.
Output Buffer Supply: +3.3V -5% and +5%.
No Connect: These signals are not internally connected.
10
11
00
01
10
11
00
01
256K X 18 FLOW-THROUGH ZBL SRAM
4
Fourth Address
Fourth Address
(internal)
(internal)
A...A
A...A
A...A
A...A
A...A
A...A
A...A
A...A
10
01
00
00
01
10
11
11
1
1
DESCRIPTION
Galvantech, Inc. reserves the right to change products or specifications without notice.
GVT71256ZB18