gvt71256zb18 ETC-unknow, gvt71256zb18 Datasheet - Page 13

• Manufacturer Part Number: gvt71256zb18
• Description: 256k Flow-through Sram
• Manufacturer: ETC-unknow

Note:
1. Q(A
2. CE2# timing transitions are identical to the CE# signal. For example, when CE# is LOW on this waveform, CE2#
3. CKE# when sampled HIGH on the rising edge of clock will block that L-H transition of the clock from propagating
4
July 23, 1998
Rev. 7/98
. Individual Byte Write signals (BWx#) must be valid on all write and burst-write cycles. A write cycle is initiated
GALVANTECH
DATA Out (Q)
BWa#, BWb#
DATA In (D)
corresponding to address A
is LOW. CE2 timing transitions are identical but inverted to the CE# signal. For example, when CE# is LOW on
this waveform, CE2 is HIGH.
into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal register in the SRAM
will retain their previous state.
when R/W# signal is sampled LOW when ADV/LD# is sampled LOW. The byte write information comes in one
cycle before the actual data is presented to the SRAM.
(See Note)
ADDRESS
ADV/LD#
1
) represents the first output from the external address A
CKE#
R/W#
CLK
OE#
CE#
A
1
t
KQ
t
KQLZ
2.
Q(A
t
t
t
t
t
t
S
S
S
1
S
S
S
)
, INC.
A
2
t
KQHZ
t
KC
t
t
KQX
t
H
t
t
t
t
H
H
H
H
H
CKE# TIMING
t
KL
256K X 18 FLOW-THROUGH ZBL SRAM
13
t
SD
D(A
1
A
. D(A
3
t
HD
2
)
t
KH
2
) represents the input data to the SRAM
Galvantech, Inc. reserves the right to change products or specifications without notice.
Q(A
3
)
GVT71256ZB18
A
4
Q(A
A
5
4
)