ax500-1cs896i Actel Corporation, ax500-1cs896i Datasheet - Page 10

ax500-1cs896i

Manufacturer Part Number

ax500-1cs896i

Description

Axcelerator Family Fpgas

Manufacturer

Actel Corporation

Datasheet

1.AX500-1CS896I.pdf (226 pages)

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Figure 1-6 • AX Device Architecture (AX1000 shown)

Embedded Memory

As mentioned earlier, each core tile has either three (in a

smaller tile) or four (in the regular tile) embedded SRAM

blocks along the west side, and each variable-aspect-

ratio SRAM block is 4,608 bits in size. Available memory

configurations are: 128x36, 256x18, 512x9, 1kx4, 2kx2 or

4kx1 bits. The individual blocks have separate read and

write ports that can be configured with different bit

widths on each port. For example, data can be written in

by eight and read out by one.

In addition, every SRAM block has an embedded FIFO

control unit. The control unit allows the SRAM block to

be configured as a synchronous FIFO without using core

logic

programmable. The FIFO also features programmable

ALMOST-EMPTY (AEMPTY) and ALMOST-FULL (AFULL)

flags in addition to the normal EMPTY and FULL flags. In

addition to the flag logic, the embedded FIFO control

unit also contains the counters necessary for the

generation of the read and write address pointers as well

1 -4

Axcelerator Family FPGAs

I/O Structure

See Figure 7

modules.

The

Chip Layout

FIFO

width

and

RAM/

FIFO

depth

RAMC

SuperCluster

are

v2.6

as control circuitry to prevent metastability and

erroneous operation. The embedded SRAM/FIFO blocks

can be cascaded to create larger configurations.

I/O Logic

The Axcelerator family of FPGAs features a flexible I/O

structure, supporting a range of mixed voltages with its

bank-selectable I/Os: 1.5V, 1.8V, 2.5V, and 3.3V. In all,

Axcelerator FPGAs support at least 14 different I/O

standards (single-ended, differential, voltage-referenced).

The I/Os are organized into banks, with eight banks per

device (two per side). The configuration of these banks

determines the I/O standards supported (see

on page 2-10

available in each bank.

Each I/O module has an input register (InReg), an output

(Figure 1-7 on page

modules, four RX modules, two TX modules, and a buffer

(B) module.

for more information). All I/O standards are

Core Tile

1-5). An I/O Cluster includes two I/O

"User I/Os"

ax500-1cs896i Actel Corporation, ax500-1cs896i Datasheet - Page 10

ax500-1cs896i

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