ax500-1cs896i Actel Corporation, ax500-1cs896i Datasheet - Page 56

• Manufacturer Part Number: ax500-1cs896i
• Description: Axcelerator Family Fpgas
• Manufacturer: Actel Corporation

Timing Characteristics
Table 2-60 • LVPECL I/O Module
2 -4 2
Parameter
LVPECL Output Module Timing
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DP
PY
ICLKQ
OCLKQ
SUD
SUE
HD
HE
CPWHL
CPWLH
WASYN
REASYN
HASYN
CLR
PRESET
Axcelerator Family FPGAs
Worst-Case Commercial Conditions V
Input Buffer
Output Buffer
Clock-to-Q for the I/O input register
Clock-to-Q for the IO output register and the I/O
enable register
Data Input Set-Up
Enable Input Set-Up
Data Input Hold
Enable Input Hold
Clock Pulse Width High to Low
Clock Pulse Width Low to High
Asynchronous Pulse Width
Asynchronous Recovery Time
Asynchronous Removal Time
Asynchronous Clear-to-Q
Asynchronous Preset-to-Q
Description
CCA
= 1.425V, V
v2.6
CCI
Min.
0.43
0.45
0.43
'–2' Speed
= 3.0V, T
Max.
1.70
0.67
0.67
0.23
0.00
0.00
0.00
0.23
0.23
2.28
0.26
0.10
J
= 70°C
Min.
0.48
0.51
0.48
'–1' Speed
Max.
1.93
0.77
0.77
0.00
0.00
0.10
0.00
0.27
0.27
2.60
0.27
0.30
Min.
0.57
0.60
0.57
'Std' Speed
Max.
2.28
3.06
0.90
0.90
0.31
0.35
0.00
0.00
0.10
0.00
0.31
0.31
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns