ax500-1cs896i Actel Corporation, ax500-1cs896i Datasheet - Page 221

• Manufacturer Part Number: ax500-1cs896i
• Description: Axcelerator Family Fpgas
• Manufacturer: Actel Corporation

Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous Version
v2.5
v2.4
v2.3
v2.2
v2.1
In
In the
information.
The
The
A note was added to
In the
Revised ordering information and timing data to reflect phase out of –3 speed grade options.
Table 2-3
The
Table 2-2
"VCCDA Supply Voltage"
"PRA/B/C/D Probe A/B/C/D"
The
Figure 1-3
Table 2-2
The
Table 2-4
Table 2-5
The
Table 2-7
Figure 2-1
The External Setup and Clock-to-Out (Pad-to-Pad) equations in the
LVTTL 24mA High Slew Clock I/O"
The External Setup and Clock-to-Out (Pad-to-Pad) in the
High Slew Clock I/O"
The
The
Table 2-17
Figure 2-8
Figure 2-13
Changes in Current Version (v2.6)
Table
"Global Resource Distribution"
" 624-Pin CCGA" table
"Packaging Data"
"User I/Os"
"Power-Up/Down Sequence"
"Timing Characteristics"
"Global Pins"
"User I/Os"
"Pin
"Package Thermal
2-4, the units for the P
was updated.
was updated.
was updated.
was updated.
was updated.
was updated.
was updated.
was updated.
was updated.
Descriptions"section, the
was updated.
and
was updated.
section was updated.
Figure 2-14
section was updated.
Table
section were updated.
section is new.
Characteristics", the temperature was changed from 150°C to 125°C.
was updated.
2-2.
was updated.
were updated.
was updated.
section was added.
LOAD
section was updated.
section were updated.
, P
section was updated.
HCLK
10
, and P
v2.6
and
I/O
CLK
were updated from mW/MHz to mW/MHz.
descriptions were updated to include tie-off
"Routed Clock – Using LVTTL 24mA
"Hardwired Clock – Using
Axcelerator Family FPGAs
3-103
Page
2-59
2-10
2-10
2-10
2-17
2-18
2-21
2-2
2-9
2-1
2-6
2-1
2-9
1-3
2-1
2-1
2-2
2-3
2-7
2-7
2-8
2-8
2-8
2-9
iii
2
4-1