ax500-1cs896i Actel Corporation, ax500-1cs896i Datasheet - Page 84
ax500-1cs896i
Manufacturer Part Number
ax500-1cs896i
Description
Axcelerator Family Fpgas
Manufacturer
Actel Corporation
Datasheet
1.AX500-1CS896I.pdf
(226 pages)
- Current page: 84 of 226
- Download datasheet (3Mb)
Adjustable Clock Delay
Figure 2-55
case, the output clock is delayed relative to the reference clock. Delaying the reference clock relative to the output
clock is accomplished by using the delay line in the feedback path.
Figure 2-55 • Using the PLL Delaying the Reference Clock
2 -7 0
Axcelerator Family FPGAs
PowerDown
FB
illustrates using the PLL to delay the reference clock by employing one of the adjustable delay lines. In this
133 MHz
RefCLK
FBMuxSel
Delay Line
Delay Line
DelayLine
5
/i Delay
Match
DividerI
6
÷1
/j
v2.6
LowFreq
PLL
3
Osc
DividerJ
/j Delay
Match
6
/j
133 MHz
Lock
CLK1
CLK2
Related parts for ax500-1cs896i
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Manufacturer:
MICROSEMI
Datasheet:
Part Number:
Description:
Axcelerator Family FPGAs
Manufacturer:
ACTEL [Actel Corporation]
Datasheet:
Part Number:
Description:
Manufacturer:
Actel Corporation
Datasheet: